Dense SOI programmable logic array structure

Details Dense SOI programmable logic array structure Dense SOI programmable logic array structure

1999-08-12

2001-02-20

Picardat, Kevin M. (Department: 2822)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

C438S164000, C438S412000, C438S479000, C438S154000

Reexamination Certificate

active

06190950

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to an improved semiconductor structure for high density device arrays, such as ROMs, programmable logic arrays or memory decode arrays. In particular, this invention relates to a Silicon-On-Insulator (SOI) array of fully isolated device islands that can be implemented with a small feature size, and a process for its formation.
BACKGROUND OF THE INVENTION
SOI technology provides many advantages when used in Complementary Metal-Oxide-Semiconductor (CMOS) Integrated Circuits (ICs). One primary advantage is a significant reduction of parasitic capacitance between a source/drain and a substrate. Other major advantages include elimination of latch-up, reduction of chip size and/or increased device density, and increased circuit speed. SOI devices also have lower power requirements and higher speeds compared to non-SOI devices, making SOI technology popular for use in battery-operated equipment.
The advantages of SOI structures result from the total isolation of the device islands from the substrate. Total isolation has been achieved using a sapphire substrate instead of a semiconductor substrate, but the resultant product is expensive and the quality of the crystalline silicon grown on sapphire is usually poor. Processes to achieve device-substrate isolation using a silicon substrate are known, but such processes may not achieve total isolation, and may cause defects in the resultant structures.
SOI structures may be formed through a variety of processes, including SIMOX, wafer bonding, FIPOS and etch and oxidation processes. Separation by Implanted Oxygen (SIMOX) involves oxygen ion implantation into a silicon substrate to form a buried oxide insulating layer. This method is expensive and has the disadvantage of damaging the crystalline structure of the silicon above the insulating layer due to the passage of high energy oxygen ions.
Wafer bonding is another technique for forming an isolation layer in a substrate. It involves the fusing together of two oxidized silicon wafers in a high-temperature furnace. However, wafer bonding is an undesirable technique because it increases the substrate thickness, and has low production yields due to voids and particles interfering with adequate bonding between the wafers.
The Full Isolation by Porous Oxidized Silicon (FIPOS) process forms an insulating layer through the initial formation of a doped layer in the silicon substrate, covered with a layer of undoped epitaxial silicon. The substrate is then anodized to create a porous layer of silicon under islands of undoped silicon in the substrate. The FIPOS process is slow and expensive, and produces a substrate with a tendency to warp or curl due to the thermal stresses it has undergone.
Another known technique used to form an isolation layer is a series of etch and oxidation steps used to create silicon islands, as described in U.S. Pat. No. 4,604,162. Islands are formed by the etching and subsequent partial undercutting of the islands. Silicon filaments maintain the connection of the islands to the substrate during the undercutting step, and the subsequent thermal oxidation step. During thermal oxidation, which creates an isolation layer under the islands, expansion of the oxide subjects the islands to substantial mechanical stress and crystal damage. The silicon filaments connecting the islands to the substrate are also under tensile stress that creates dislocations of the islands, resulting in high junction leakage and low carrier mobility.
In addition to the isolation of the devices from the substrate, it is also important to isolate the devices from each other. The use of silicon device islands with isolation trenches is known, but such devices typically do not have a high functional density. As the minimum feature size decreases, the number of devices in a chip area (active device density) increases, but the area occupied by interconnection lines on the chip surface minimizes the number of interconnected devices in a chip area (functional density). To be effective, a high density device array should maximize both active device density and functional density.
There is a need for a fully isolated high density semiconductor structure suitable for use in, e.g., ROMs, programmable logic arrays, or memory decode arrays.
SUMMARY OF THE INVENTION
The present invention provides a fully isolated semiconductor structure that has a high density and is suitable for use in ROMs, programmable logic arrays, or memory decode arrays. The present invention permits effective isolation between devices and reduces the area occupied by interconnection lines on the device surface.
In addition, the present invention provides a process for fabricating an isolated structure that minimizes damage to the structure and avoids dislocations during the isolation process.
Advantage and features of the present invention will be apparent from the following detailed description and drawings which illustrate preferred embodiments of the invention.


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