Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-06-30
2001-12-11
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S329000
Reexamination Certificate
active
06329236
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a semiconductor memory device; and, more particularly, to a method for fabricating a resistive load SRAM, which is capable of providing a high resistive load without local resistance variation.
DESCRIPTION OF THE PRIOR ART
There are two types of semiconductor memories: non-volatile and volatile, and there are two types of volatile random access memory (RAM): static and dynamic. The dynamic RAM (DRAM) is widely used as a main memory and the static RAM (SRAM) is usually used as cache memory.
As is well known, memory cells contained in a SRAM memory arrays are arranged in rows and columns in a form of matrix. Currently, there are several types of memory cells, such as a six transistor memory cell, four transistor memory cell with resistive load and four transistor memory cell with TFT-load, and the like.
Referring to
FIGS. 1A
to
1
C, there are illustrated schematic diagrams showing sequential steps of fabricating a conventional resistive load SRAM.
As shown in
FIG. 1A
, a device isolation layer
10
is formed on a substrate
16
, and then a step for providing driver and access transistors is processed. Thereafter, an oxide layer
12
is deposited on the substrate
16
for isolation, and a butting contact (or node contact) region
13
is then provided by selectively etching the oxide layer
12
. A reference number
11
illustrates a doped polysilicon layer, which composes gates of the driver and the access transistors.
Referring to
FIG. 1B
, an undoped polysilicon layer
14
is deposited on a resulting structure having the butting contact region
13
to a thickness of about 800 Å. Then, arsenic ions (As) are inserted into the undoped polysilicon layer
14
through the use of blanket ion implantation in order for the layer
14
to have around tens of gigaohm (G&OHgr;) resistance.
Referring to
FIG. 1C
, a photoresist pattern
15
covering a region for high load resistor is then formed on the polysilicon layer
14
. By using the photoresit pattern
15
as an ion implantation mask, V
cc
ion implantation is performed to reduce the resistance of a region of the polysilicon layer
14
for V
cc
line and butting contact region. Then, the polysilicon layer
14
is patternized to provide V
cc
line, butting contact and high load resistor.
At this time, when a blanket ion implantation is processed for the undoped polysilicon layer to have high resistance after an undoped polysilicon layer is deposited, a selective ion implantation is performed to reduce resistance of a region for V
cc
line and butting contact.
However, when the masking process for butting contact is not well aligned, the polysilicon layer
14
has locally different resistance.
FIG. 2
illustrates a scanning electron microscope (SEM) picture showing butting contact. As shown, since the butting contact is provided as a pair, when the masking process for the butting contact is not aligned, two bottom portions A and B (shown in
FIG. 1A
) of the butting contact region have different width. In this case, the thickness C and D (shown in
FIG. 1B
) of the polysilicon layer
14
at the two bottom portions of butting contact region
13
are different and thus the polysilicon layer
14
has locally different resistance after the V
cc
ion implantation. It is very difficult, if not impossible, to solve above mentioned resistance difference with improvement of masking process for butting contact.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a method for fabricating a resistive load SRAM, which is capable of providing a high resistive load without local resistance variation.
In accordance with an as aspect of the present invention, it is provided a method for fabricating a resistive load static random access memory (SRAM), comprising the steps of: a) forming an isolated layer on a semiconductor substrate having driver and access transistors provided thereto; b) selectively etching said isolated layer to provide a butting contact region; c) forming a doped polysilicon layer on a resulting structure; d) selectively counter-doping said doped polysilicon layer; and e) patterning said doped polysilicon layer to provide a power supply line, a butting contact and a high load resistor.
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Choi Ik-Soo
Kang Byoung-Ju
Blakely & Sokoloff, Taylor & Zafman
Hyundai Electronics Industries Co,. Ltd.
Nelms David
Nhu David
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