Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-06-09
2001-10-16
Trinh, Michael (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S563000, C438S301000
Reexamination Certificate
active
06303453
ABSTRACT:
BACKGROUND OF THE INVENTION
The invention relates to a method of manufacturing a semiconductor device comprising a MOS transistor, for brevity hereinafter generally referred to as MOST (=Metal Oxide Semiconductor Transistor), in which method a gate oxide and a gate electrode are formed on a surface of a semiconductor body of silicon, a source region and a drain region being formed in the semiconductor body on either side of the gate electrode, a part of said source and drain regions bordering on the edge of the gate electrode, for brevity hereinafter generally referred to as LDD (=Lightly Doped Drain) region, being provided with a lower doping concentration, and on either side of the gate electrode, the surface of the semiconductor body being provided with a dielectric layer, the part of which bordering on the surface of the semiconductor body being obtained by thermal oxidation of the semiconductor body, and the more heavily doped parts of the source region and of the drain region being formed by providing a spacer on either side of the gate electrode and subsequently doping the semiconductor body with suitable doping atoms by means of an ion implantation. In practice, generally both the source region and the drain region are provided with an LDD region.
Such a method is used, in particular, in the manufacture of ICs (=Integrated Circuits) wherein MOS, CMOS or BICMOS circuits are incorporated. The MOS transistor serves, for example, as a switch but may alternatively be embodied so as to be a memory element. The LDD regions preclude, or at least limit, the development of hot charge carriers in that they limit the size of the maximum lateral electric field. The importance hereof increases steadily as the dimensions of the MOS transistors decrease continually.
A method of the type mentioned in the opening paragraph is known from United States patent specification U.S. Pat. No. 5,702,986, published on Dec. 30, 1997. The manufacture of a MOST in a silicon substrate is described by means of
FIG. 1
of said patent specification, in which a more heavily doped part of the source and drain regions is formed by doping the substrate with doping atoms by means of an ion implantation after the gate electrode formed is provided with a spacer on both sides. Prior to this process step, the surface of the semiconductor body is provided, on either side of the gate electrode formed, with a dielectric layer, in this case a silicon dioxide layer, whose formation is partly due to reoxidizing the semiconductor surface after the formation of the gate electrode, and the silicon substrate is doped with doping atoms on either side of the gate electrode by means of an ion implantation at a lower implantation energy and/or implantation flux, thereby forming the LDD regions. After both implantations, a temper step takes place in which, at the location of both the more heavily and the more lightly doped parts of the source and drain regions, the crystal damage in the silicon substrate is repaired, and in which step the doping atoms are rendered electrically active.
A drawback of the known method is that the MOST manufactured thereby still suffers from the above-mentioned “short-channel” effects, which manifest themselves, inter alia, in that the threshold voltage of the MOST manufactured decreases substantially for very short lengths of the gate electrode, which is undesirable.
SUMMARY OF THE INVENTION
Therefore, it is an object of the invention to provide a method of the type mentioned in the opening paragraph, in which the above-mentioned drawback is obviated or at least substantially reduced, and which method consequently enables short-channel effects, such as a substantial dependence of the threshold voltage upon the length of the gate electrode, to be more strongly suppressed in a MOST. In addition, the method should be as simple as possible.
To achieve this, a method of the type mentioned in the opening paragraph is characterized in that the lightly doped part of the source and drain regions is obtained by doping, in a first step, the dielectric layer with suitable doping atoms by means of a second ion implantation, the implantation conditions being chosen to be such that after the second ion implantation substantially all doping atoms are situated within the dielectric layer, and, in a second step, a part of the doping atoms is diffused from the dielectric layer into the semiconductor body, resulting in the formation of the more lightly doped part of the source region and the drain region. The invention is based on a number of surprising realizations. Since the doping atoms necessary to form the LDD regions are implanted in the dielectric layer, the quantity of doping atoms available for this purpose can be adjusted very accurately and reproducibly, resulting in a very accurate and reproducible method. In addition, since the doping atoms do not (yet) find their way to the semiconductor body, crystal damage to the semiconductor body is precluded, so that an irregular and accelerated diffusion in a tempering step, which step is necessary in such a case, does not occur in a method in accordance with the invention. In a second step, a part of the doping atoms available in the dielectric layer are diffused in the semiconductor body, resulting in LDD regions having a very steep and very shallow doping profile. By virtue thereof, the MOST manufactured has excellent properties, such as a threshold voltage which is relatively independent of the length of the gate electrode. The invention is further based on the recognition that the thin dielectric layers generally present in a MOST, such as layers of silicon dioxide, silicon nitride and silicon oxynitride, constitute a very suitable diffusion source for the formation of the LDD regions. It has surprisingly been found that the method in accordance with the invention is very accurate and reproducible, provided that the first part of the dielectric layer used for the second implantation and the subsequent diffusion step consists of (thermally produced) silicon dioxide. In the second ion implantation, ions may penetrate the dielectric layer nearly as far as the surface of the semiconductor body; this even has a favorable effect on the formation of very shallow and steep LDD regions with a minimum heat supply during the diffusion step. It is important that the quantity of atoms reaching the semiconductor body during the ion implantation is so small that no, or hardly any, crystal damage occurs in the semiconductor body. However, the implanted profile may also be situated at a small distance, for example a few nanometers, from said surface. Finally, the invention is based on the recognition that the equipment necessary for ion implantation can be currently provided with the means for carrying out an ion implantation at a very low implantation energy.
In a preferred embodiment of a method in accordance with the invention, the dielectric layer is formed simultaneously with the gate oxide. In addition to excellent results obtained by using such a dielectric layer, such a method is very simple and links up well with the customary MOS technology. Preferably, the dielectric layer is formed by thickening the gate oxide on either side of the gate electrode by means of a thermal oxidation. In practice it has been found that very suitable thicknesses of the dielectric layer range between 2 and 20 nm, preferably between 2 and 10 nm. In this respect, the flux of the second ion implantation can be chosen to range between 10
14
and 10
16
at/cm
−2
, and the implantation energy can be chosen to range between 0.1 and 5 keV.
In a first variant of the methods described hereinabove, the second ion implantation is carried out prior to the provision of the spacers, whereafter the first ion implantation is carried out. This variant is very suitable because the spacers, which can be advantageously used for a so-called silicide process, remain intact. In another variant, after the provision of the spacers and carrying out the first ion implantation, said spa
Schmitz Jurriaan
Woerlee Pierre H.
Biren Steven R.
Trinh Michael
U.S. Philips Corporation
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