Method of forming salicide in embedded dynamic random access...

Details Method of forming salicide in embedded dynamic random access... Method of forming salicide in embedded dynamic random access...

1998-12-08

2001-05-01

Le, Vu A. (Department: 2824)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S229000, C438S231000, C438S649000, C438S721000

Reexamination Certificate

active

06225155

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor process. More particularly, the present invention relates to a method of forming a salicide layer in an embedded dynamic random access memory (DRAM).
2. Description of Related Art
An embedded dynamic random access memory (DRAM) has a logic region and a random access memory region (called memory region hereinafter). A gate of a traditional logic region comprises an N-type metal oxide semiconductor field effect transistor (n-MOSFET) formed from N-type doped polysilicon and P-type MOS field effect transistor (p-MOSFET) to form a CMOS structure. The phenomenon of punch through and turnoff characteristics are easily generated in a PMOS with an N-type doped polysilicon gate. Therefore, an NMOS having an N-type polysilicon gate and a dual gate of PMOS having an P-type polysilicon gate are gradually used in the logic region to lower the bad effects mentioned above.
A salicide layer cannot be formed on a source/drain region of an embedded DRAM in order to avoid serious current leakage occurring on the source/drain region of the embedded DRAM. Therefore, a tungsten silicide layer is provided on a polysilicon layer to lower resistance of the gate and to increase conductivity of the gate. However, some problems also arise when a dual gate of the embedded DRAM is formed by the tungsten silicide layer on the polysilicon layer to reduce the resistance of the dual gate, as shown in
FIGS. 1A
to
1
D.
FIGS. 1A
to
1
D are schematic, cross-sectional views showing a conventional method of fabricating an embedded DRAM. Referring to
FIG. 1A
, a gate oxide layer
102
and a polysilicon layer
104
are sequentially formed on a substrate
100
. Ion implantation steps using N-type ions and P-type ions are respectively performed in the polysilicon layer
104
, using a mask. A tungsten silicide layer
106
is formed on the polysilicide layer
104
to increase conductivity of a gate formed in a later process. The tungsten silicide layer
106
, a dual gate
108
a
and a gate
108
b
are formed by defining the tungsten silicide layer
106
, the polysilicon layer
104
and the gate oxide layer
102
, as shown in FIG.
1
B.
FIG. 2
is a schematic, three-dimensional diagram showing a dual gate
108
a
and a gate
108
b
according to FIG.
1
B. The dual gate
108
a
has an N-type polysilicon layer
104
a′
and a P-type polysilicon layer
104
a″.
The gate
108
b
has an N-type polysilicon layer
104
b.
An N-type doped drain (LDD) region
110
and P-type LDD region
110
are respective formed in the substrate
100
. Silicon nitride spacers
112
are formed on sidewalls of the gates
108
a,
108
b.
An ion implantation step is performed in the substrate
100
to respectively form an N-type source/drain region
114
and P-type source/drain region
114
. A rapid thermal process (RPT) is performed at about 1000° C. to activate ions of the source/drain regions
114
.
As shown in
FIG. 1C
, the substrate
100
is covered with an oxide layer
116
. The oxide layer
116
is defined using a mask to make the oxide layer
116
cover only a portion of the substrate
100
. The portion not covered with the oxide layer
116
is defined as a logic region
118
a,
and the other portion covered with the oxide layer
116
is defined as a memory region
118
b.
A titanium layer is formed over the substrate
100
. A RTP is performed to make the titanium layer to react with the exposed substrate
100
. Titanium silicide layers
120
are formed on the exposed source/drain region
114
in the logic region
118
a,
as shown in FIG.
1
D.
In the process mentioned above, the purpose of forming the tungsten silicide layer
106
is to increase conductivity of the polysilicon layer
104
. While performing the RTP, the high temperature and larger diffusion coefficient of impurities in the tungsten silicide layer will lead to some bad effects for the dual gate in the logic region. Due to the conditions mentioned above, the N-type impurities in the polysilicon layer
104
a′
of the dual gate diffuse into the P-type polysilicon layer
104
a″
through the tungsten silicide layer
106
. The P-type impurities in the polysilicon layer
104
a″
also diffuse into the N-type polysilicon layer
104
a′
through the tungsten silicide layer
106
. Thus, inter-diffusion occurs in the dual gate, as shown in FIG.
2
. The inter-diffusion will cause the dual gate to fail.
In addition, a definition step must be performed on the tungsten silicide layer
106
and the polysilicide layer
104
in order to form the gate. It is more difficult to perform the definition step due to the presence of the tungsten silicide layer
104
.
SUMMARY OF THE INVENTION
Accordingly, the present invention provides a method for avoiding inter-diffusion in a dual gate to ensure reliability of a device.
Another aspect of the invention is to form a salicide layer on a gate, a source/drain region in a logic region, and on a gate in a memory region in order to increase conductivity of the gates.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method of forming a salicide layer in an embedded DRAM. A dual polysilicon gate is formed on a substrate in a logic region, and a gate is formed on a substrate in a memory region. An insulating layer, a hard material layer and a dielectric layer are sequentially formed over the substrate. An etching back process, a definition process and an etching process are sequentially performed to expose the dual gate and the source/drain region in the logic region and the gate in the memory region. Salicide layers are formed on the exposed dual gate, the exposed source/drain region in the logic region and the exposed gate in the memory region. An annealing process is performed on the source/drain region before forming the salicide layers, therefore, the thermal process will not be performed in the later processes. Inter-diffusion and thermal instability problems can be avoided. Therefore, the invention provides a method for increasing conductivity of the gates to form the salicide layers on the dual gate, the source/drain region in the logic region, and the gate in the memory region.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 5508212 (1996-04-01), Wang et al.
patent: 5691212 (1997-11-01), Tsai et al.
patent: 5963829 (1999-10-01), Matsubara
patent: 6020240 (2000-02-01), Wu
patent: 6025274 (2000-02-01), Lin et al.
patent: 6030863 (2000-02-01), Chang et al.
patent: 6037204 (2000-03-01), Chang et al.

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