Semiconductor device and manufacturing method thereof

Details Semiconductor device and manufacturing method thereof Semiconductor device and manufacturing method thereof

1999-09-20

2001-12-25

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S291000, C438S369000, C438S655000, C438S151000, C438S153000, C257S337000, C257S338000, C257S350000, C257S351000

Reexamination Certificate

active

06333222

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device having a plurality of MIS (Metal Insulator-Semiconductor) transistors with different electric characteristics and a manufacturing method thereof.
2. Description of the Background Art
As a method for improving system performance, System on Chip technology has been actively researched and developed recently. A device particularly drawing attention is a DRAM mixed logic memory device in which a memory portion with large capacity and a logic portion operating at high speed are mounted on a single chip.
In the DRAM mixed logic memory device, an MIS transistor is one of technically important key devices. Specifically, in the DRAM memory cell portion, the MIS transistor must be very small to minimize the size of the memory cell and must include an insulation film capable of enduring high voltage application to accommodate a voltage of a word line of a level higher than power supply voltage.
Conversely, in the DRAM logic portion, as high-speed operation is required, a gate electrode interconnection and source/drain active regions must have low resistance and high current driving capability.
To meet the above described conflicting requirements in the DRAM mixed logic memory device is not easy, and generally the performance of the MIS transistor in the DRAM logic portion is lowered to be equal to the performance of the MIS transistor in the DRAM memory cell portion.
FIGS. 14A and 14B
show sectional structures of N type MIS transistors, respectively in the memory cell portion and the logic portion mounted on separate chips according to a conventional art.
Shown in
FIGS. 14A and 14B
are, a semiconductor substrate
1
a
, a P type well region
2
a
, a trench isolation region
3
a
, gate insulation films
4
a
and
4
b
of silicon oxide films or the like, a first polycrystalline silicon film
5
a
of a polycrystalline silicon film doped with an N type impurity or the like, a second polycrystalline silicon film
5
b
of an N type polycrystalline silicon film doped with an impurity by ion implantation after the formation of the polycrystalline silicon film, a first silicide layer
6
a
of a tungsten silicide (WxSiy) layer or the like, a second silicide layer
6
b
of a titanium silicide, (TixSiy) layer, cobalt silicide (CoxSiy) layer or the like, N− source/drain active regions
7
a
, an extension region
7
b
, N+ source/drain active regions
8
a
, insulation films
9
a
and
9
c
of a silicon nitride film, a silicon nitrided oxide insulation film, or the like, an insulation film
9
b
of a silicon nitrided oxide film, a silicon oxide film (both will be referred to as silicon oxide film hereinafter) or the like, and a third silicide layer
10
of a titanium silicide (TixSiy) layer, a cobalt silicide (CoxSiy) layer or the like formed as a silicide layer on the active region.
First polycrystalline silicon film
5
a
and first silicide layer
6
a
form a gate electrode of a first MIS transistor of the memory cell portion. Second polycrystalline silicon film
5
b
and second silicide layer
6
b
form a gate electrode of a second MIS transistor of the logic portion.
Insulation film
9
c
covers the gate electrode of the first MIS transistor of the memory cell portion and insulation film
9
b
is a sidewall.
In general, the performance of the MIS transistor is improved with a thinner gate insulation film. On the other hand, when the gate insulation film is thin, a voltage applied to the gate is lowered to guarantee the reliability. Therefore, in the memory cell portion where high voltage operation is required, thick gate insulation film
4
a
is formed whereas in the logic portion where maintenance of a certain level of the performance rather than the high voltage operation is required, thin gate insulation film
4
b
is formed.
In addition, as the logic portion rather than the memory cell portion must operate at fast speed, a material employed in a silicide has a lower sheet resistance at an electrode interconnection in the logic portion than in the memory cell portion. Additionally, the active region is formed of a silicide to suppress the delay of the transistor operation caused by parasitic resistance.
With reference to
FIGS. 15A and 15B
, sectional structures of the memory cell portion and the logic portion of the DRAM chip having the above described DRAM mixed logic memory will be described. In the drawings, though the structure is shown only up to a level of a first metal interconnection
26
(described below) for the simplicity, generally about two to six layers of metal interconnections are employed besides first metal interconnection
26
.
The memory cell portion shown in
FIG. 15A
includes, a bit line
21
formed of polycrystalline silicon, a polycide or the like, a storage node
22
formed of polycrystalline silicon or the like, a capacitor dielectric film
23
formed of a silicon oxide film, a silicon nitrided oxide film or the like, and a cell plate
24
formed of polycrystalline silicon or the like. In addition, the structure includes interlayer insulation films
28
a
,
29
and
30
.
In the logic portion shown in
FIG. 15B
, an N type MIS transistor region
25
n
of a second MIS transistor and a P type MIS transistor region
25
p
of a third MIS transistor are arranged. Further, in P type MIS transistor region
25
p
, a third polycrystalline silicon film
5
c
of a P type polycrystalline silicon film doped with an impurity through ion implantation after the formation of the polycrystalline silicon film and a second silicide layer
6
c
of a silicide layer formed on third polycrystalline silicon film
5
c
are formed. Still further, in P type MIS transistor region
25
p
, a first metal interconnection
26
, and metal plugs
27
connecting first metal interconnection
26
and the active region, and first metal interconnection
26
and the gate electrode (not shown) of the transistor are formed. In some cases, first metal interconnection
26
and metal plug
27
are employed also in the memory cell portion. An interlayer insulation film
28
b
is also provided.
Next, a method for manufacturing first and second MIS transistors in a memory cell portion and a logic portion of a DRAM mixed logic memory will be described. Here the manufacturing processes up to the formation of interlayer insulation film
28
a
shown in
FIG. 15
will be described and the process after the formation of interlayer insulation film
28
a
will not be described. In addition, as a manufacturing process of a third MIS transistor, which is a P type MIS transistor, is the same with that of first and second MIS transistor, the description thereof will not be repeated.
With reference to
FIG. 16
, P type well region
2
a
and an N type well region
2
c
(see
FIG. 15
) are formed on semiconductor substrate
1
a.
Then, trench isolation region
3
a
is formed in a region reaching a certain depth from a surface of P type well region
2
a
. After the memory cell portion is covered by a resist film
32
, a silicon oxide film is formed as gate insulation film
4
b
of the logic portion in the thickness range of about 2 to 4 nm. Thereafter polycrystalline silicon film
5
b
not doped with an impurity and a silicon oxide film
31
are formed.
Then, anisotropic etching is performed on silicon oxide film
31
by the photolithography technique. Thereafter anisotropic etching is performed on polycrystalline silicon film
5
b
and gate insulation film
4
b
using silicon oxide film
31
as a mask, and the gate electrode pattern of the logic portion is formed.
Then implantation of an n type impurity is performed respectively on the N type MIS transistor and P type MIS transistor of the logic portion, forming n type extension region
7
b
and an n type extension region
7
c
(see FIG.
15
).
As shown in
FIG. 17
, after the removal of silicon oxide film
31
on the gate electrode through the wet etching or the like, insulation film
4
a
of a silicon oxide film or the like is formed. In addition, sidewall
9

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