Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1998-11-04
2001-02-20
Booth, Richard (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
Reexamination Certificate
active
06190968
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to EPROM and flash memory cells and, more particularly, EPROM and flash memory cells with source-side injection.
2. Description of the Related Art
An electrically-programmable read-only-memory (EPROM) cell and a flash memory cell are non-volatile memories that retain data stored in the cell after power to the cell has been removed. EPROM and flash memory cells principally differ from each other in that EPROM cells are erased with ultraviolet (UV) light, while flash cells are electrically erased.
FIG. 1
shows a cross-sectional view that illustrates a prior art EPROM or flash memory cell
100
. As shown in
FIG. 1
, cell
100
includes spaced-apart n+ source and drain regions
112
and
114
which are formed in a p-type substrate
110
, and a channel region
116
which is defined in substrate
110
between source and drain regions
112
and
114
.
In addition, cell
100
also includes a layer of gate oxide
120
which is formed over channel region
116
, and a floating gate
122
which is formed over gate oxide layer
120
. Further, cell
100
additionally includes a layer of interpoly dielectric
124
which is formed over floating gate
122
, and a control gate
126
which is formed over dielectric layer
124
.
Cell
100
is programmed by applying a programming voltage to control gate
126
, a drain voltage to drain region
114
, and ground to source region
112
. The programming voltage applied to control gate
126
induces a positive potential on floating gate
122
which, in turn, attracts electrons to the surface of channel region
116
to form a channel
130
.
In addition, the source-to-drain voltage sets up an electric field which causes electrons to flow from source region
112
to drain region
114
via channel
130
. As the electrons flow to drain region
114
, the electric field, which has a maximum near drain region
114
, accelerates these electrons into having ionizing collisions that form channel hot electrons near drain region
114
.
A small percentage of the channel hot electrons are then injected onto floating gate
122
via gate oxide layer
120
. Cell
100
is programmed when the number of electrons injected onto floating gate
122
is sufficient to prevent channel
130
from being formed when a read voltage is subsequently applied to control gate
124
.
Since only a small percentage of the channel hot electrons are injected onto floating gate
122
, channel hot electron programming provides a relatively low injection efficiency. One technique for increasing the injection efficiency is to create a source-to-drain electric field which, in addition to having a peak near the drain region, also has a peak near the source region. EPROM and flash memory cells which utilize an electric field which has a peak near the source region are typically referred to as having source side injection.
One way of forming an electric field which has a peak near both the source and drain regions, as described in U.S. Pat. No. 4,652,897 to Okuyama et al., is to use a low-density source region which is adjacent to the source region.
FIG. 2
shows a cross-sectional view that illustrates a prior-art, source-side injection EPROM or flash memory cell
200
.
FIG. 2
is similar to
FIG. 1 and
, as a result, utilizes the same reference numerals to designate the structures which are common to both cells.
As shown in
FIG. 2
, source-side cell
200
differs from cell
100
in that cell
200
also includes a n-type low-density source (LDS) region
210
which is formed between source region
112
and channel region
130
. LDS region
210
has a dopant concentration which is less than the dopant concentration of source region
112
.
In operation, cell
200
is programmed the same as cell
100
except that the presence of LDS region
210
causes the source-to-drain electric field to have peaks near both the LDS and drain regions
210
and
114
. As a result, channel hot electrons are formed and injected onto floating gate
122
near both of these regions
210
and
114
, thereby increasing the injection efficiency.
FIG. 3
shows a graph that illustrates the intensity of the electric field along the surface of the channel region between the drain and source regions of cell
200
. As shown in
FIG. 3
, line LO illustrates that cell
200
has a peak in the intensity of the electric field near both the drain and source regions.
One disadvantage of cell
200
, however, is that as a result of LDS region
210
, cell
200
consumes significantly more silicon real estate than does cell
100
. Thus, there is a need for an EPROM or flash memory cell that provides an increased injection efficiency with reduced cell size.
SUMMARY OF THE INVENTION
The present invention provides a method for forming a memory device having electrically-programmable read-only-memory (EPROM) or flash memory cells with both source-side and drain-side injection. The memory cells obtain a reduced cell size by forming the memory cells along the sides of trenches.
The method of the present invention begins by forming a plurality of trenches in a semiconductor material of a first conductivity type. The plurality of trenches define a plurality of top surface strips and have a plurality of bottom surfaces and sidewall surfaces such that each trench has a bottom surface and a pair of sidewall surfaces which connect the bottom surface to the adjoining top surface strips.
Once the trenches have been formed, a layer of gate oxide is formed over the top surface strips, the bottom surfaces, and the sidewall surfaces. Next, a layer of first polysilicon (poly-1) is formed on the gate oxide layer. A layer of interpoly dielectric is then formed on the poly-1 layer, followed by the formation of a second layer of polysilicon (poly-2) on the interpoly dielectric layer.
After the layer of poly-2 has been formed, the poly-2 layer, the layer of interpoly dielectric, and the layer of poly-1 are selectively etched to form a plurality of stacked gates structures where each stacked gate structure has a floating gate and a control gate.
A better understanding of the features and advantages of the present invention will be obtained by reference to the following detailed description and accompanying drawings which set forth an illustrative embodiment in which the principals of the invention are utilized.
REFERENCES:
patent: 4652897 (1987-03-01), Okuyama et al.
patent: 4929988 (1990-05-01), Yoshikawa
patent: 5204835 (1993-04-01), Eitan
patent: 5297082 (1994-03-01), Lee
patent: 5445981 (1995-08-01), Lee
patent: 5488244 (1996-01-01), Quek et al.
patent: 5502321 (1996-03-01), Matsushita
patent: 5557567 (1996-09-01), Bergemont et al.
patent: 5574685 (1996-11-01), Hsu
patent: 5596213 (1997-01-01), Lee
patent: 5780341 (1998-07-01), Ogura
Houdt, J.V. et al., “HIMOS—A High Efficiency Flash E2PROM Cell for Embedded Memory Applications,” IEEE Transactions on Electron Devices, vol. 40, No. 12, Dec. 1993, pp. 2255-2263.
Houdt, J.V. et al., “A 5 V-Compatible Flash EEPROM Cell with Microsecond Programming Time for Embedded Memory Applications,” IEEE Transactions on Components, Packaging and Manufacturing Technology—Part A, vol. 17, No. 3, Sep. 1994, pp.380-389.
Houdt, J.V. et al., “Investigation of the Soft-Write Mechansim in Source-Side Injection Flash EEPROM Devices,” IEEE Electron Device Letters, vol. 16, No. 5, May 1995, pp. 181-183.
Houdt, J.V. et al., “An Analytical Model for the Optimization of Source-Side Injection Flash EEPROM Devices,” IEEE Transactions on Electron Devices, vol. 42, No. 7, Jul. 1995, pp. 1314-1320.
Houdt, J.V. et al., “Investigation and Suppression of the Gate Disturb Effect in Source-Side Injection Flash Eeprom Arrays,” IMEC -Kapeldreef 75 -B3001 Leuven—Belgium, 4 pages.
Houdt, J.V. et al., “Subthreshold Source-side Injection (S3I): A Promising Programming Mechanism for Scaled-Down, Low Power Flash Memories” Proc. ESSDERC, 1996, pp. 131-134.
Houdt, J.V. et al., “The High Injection MOS cell: a novel 6V-only Flash EEPROM Concept with 1&mgr;s Programming Time
Bergemont Albert
Kalnitsky Alexander
Pichler Christoph
Booth Richard
Limbach & Limbach L.L.P.
National Semiconductor Corporation
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