Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-02-02
2001-10-23
Booth, Richard (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S594000
Reexamination Certificate
active
06306708
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a fabrication method for a semiconductor device, and more particularly, the present invention related to a fabrication method for an electrically erasable programmable read only memory (EEPROM) or a flash electrically erasable programmable read only memory (FLASH EEPROM).
2. Description of Related Art
The operation of a split-gate FLASH EEPROM can be performed by channel hot electron injection (CHEI) from a source to a floating gate. In such a method, a high source-to-floating gate coupling ratio is required in order to couple a high voltage from the source side to the floating gate side.
FIGS. 1
is a schematic, cross-sectional top view of a split-gate flash memory device according to the prior art. The structure of the split-gate flash memory device includes a substrate
10
, comprising a source region
18
and a drain region
20
. A gate oxide layer
12
, a floating gate
14
, a dielectric layer
16
, and a control gate
18
are formed in sequence on the substrate
10
.
However, a high source-to-floating gate coupling ratio needs a wide source
18
junction to floating gate
14
overlapped region
22
to provide electrons with enough energy to inject into the floating gate
14
. That is, a very deep source junction is required. Unfortunately, the very deep source junction causes a restriction when scaling a cell down.
Therefore, the present invention provides a stacked source structure, which is applicable on a split-gate flash memory device. A stacked source structure provides a wide vertical interface between a source junction and a floating gate, and keeps the overlap between the stacked source structure of horizontal direction and floating gate as minimum as possible. Hence, the invention can greatly improve the capability for scaling the split-gate flash memory device down.
The invention provides a split-gate flash memory that has a stacked source structure with a source coupling with a plurality of floating gates. The stacked source structure comprises a source in the substrate and a vertical polysilicon pillar formed on the source in order to increase the source-to-floating gate coupling ratio. The stacked source structure has a vertically extended polysilicon pillar on the substrate, the vertical interface area between the stacked source structure and a floating gate is increased, and the overlap between the stacked source structure of horizontal direction and the floating gate is kept as minimum as possible. Hence, the invention can greatly improve the capability for scaling the split-gate flash memory device down. Meanwhile, the polysilicon pillar is at least shared by two floating gate.
From the other point of view, the method for fabricating the split-gate flash memory having the stacked source structure comprises providing a substrate, forming a doped polysilicon pillar on the substrate, and forming a source in the substrate beneath the doped polysilicon pillar.
According to a preferred embodiment of the present invention, the method for fabricating the doped polysilicon pillar comprises the following steps. A substrate is provided. An oxide layer is formed on the substrate. A trench is formed in the oxide layer to expose the substrate area designated for a source. A polysilicon layer fills with the trench. Ions are implanted into the polysilicon layer and the substrate area designated for the source. Then, the portion of the polysilicon layer is removed to form a doped polysilicon pillar.
In addition, an annealing process is performed to drive the ions into the substrate to form a source. Then, the oxide layer is removed. A first dielectric layer is formed to cover the polysilicon pillar and the substrate. A first doped polysilicon layer is deposited on the substrate, then the first doped polysilicon layer is patterned to form a floating gate, and the exposed first dielectric layer is removed. A second conformal dielectric layer covering the float gate and the substrate is formed on the substrate. Thereafter, a second doped polysilicon layer is formed on the substrate and then patterned into a control gate. Finally, a drain is formed in the substrate.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5350937 (1994-09-01), Yamazaki et al.
patent: 5379255 (1995-01-01), Shah
patent: 5460988 (1995-10-01), Hong
patent: 5563083 (1996-10-01), Pein
patent: 5569615 (1996-10-01), Yamazaki et al.
patent: 5616510 (1997-04-01), Wong
patent: 5869369 (1999-02-01), Hong
patent: 5953605 (1999-09-01), Kodama
patent: 5969384 (1999-10-01), Hong
patent: 5990509 (1999-11-01), Burns, Jr. et al.
patent: 5998261 (1999-12-01), Hofmann et al.
patent: 6093606 (2000-07-01), Lin et al.
Booth Richard
Huang Jiawei
J.C. Patents
United Microelectronics Corp.
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