Method of making a semiconductor device with sidewall...

Details Method of making a semiconductor device with sidewall... Method of making a semiconductor device with sidewall...

2000-10-17

2001-10-30

Elms, Richard (Department: 2824)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S253000, C438S396000, C257S306000

Reexamination Certificate

active

06309931

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device and a method of manufacturing the same. It particularly relates to a memory cell structure of a DRAM (Dynamic Random Access Memory) and a method of manufacturing the same.
2. Description of the Background Art
In a DRAM, application of a buried bit line type of memory cells, where a bit line is positioned in a layer below a storage node (a lower electrode) of a capacitor, decreases limitations on the planar layout of the storage node. Accordingly, the buried bit line type of memory cells advantageously allow a large storage node capacity.
In this case, however, the bit line and a gate electrode layer of a transfer gate transistor exist in the layer below the storage node. Therefore, a contact hole for electrically connecting the storage node to the source/drain regions of the transfer gate transistor must be arranged avoiding the bit line or the like. Such an arrangement of the storage node contact will complicate the shape of a field active region and increase the size of a memory cell.
A technique for preventing the increase in size of the memory cell is disclosed, for example, in Japanese Patent Laying-Open No. 1-243573. The structure disclosed therein will now be described as a conventional semiconductor memory device.
FIG. 46
is a partial plan view schematically illustrating the structure of the conventional semiconductor memory device.
FIGS. 47 and 48
are schematic cross sectional views taken along the lines XLVII—XLVII and XLVIII—XLVIII of
FIG. 46
, respectively.
Referring to
FIGS. 46-48
, the memory cells for this DRAM have one transistor—one capacitor structure.
An element-isolating insulating film
3
a
is formed on a surface of p-type silicon substrate
1
to define an active region
2
. A p
+
channel stopper region
3
b
is formed on the lower side of element-isolating insulating film
3
a.
An MOS (Metal Oxide Semiconductor) transistor
10
serving as a transfer gate transistor is formed at active region
2
. MOS transistor
10
has a pair of n-type source/drain regions
5
,
5
, a gate insulating layer
7
and a gate electrode layer
9
. The paired n-type source/drain regions
5
,
5
are formed on a surface of p-type silicon substrate
1
such that they are spaced apart from each other by a predetermined distance. Gate electrode layer
9
is formed on a region between the paired source/drain regions
5
,
5
with gate insulating layer
7
interposed.
An interlayer insulating film
11
is formed to cover MOS transistor
10
. Formed in interlayer insulating film
11
is a contact hole
13
reaching one of the paired source/drain regions
5
. A bit line
15
is formed such that it electrically connects to n-type source/drain regions
5
through contact hole
13
and extends on interlayer insulating layer
11
.
An interlayer insulating layer
17
is formed to cover bit line
15
. A contact hole
19
reaching the other of the paired source/drain regions
5
is formed in interlayer insulating layer
11
,
17
. A capacitor
30
is formed on interlayer insulating layer
17
to be electrically connected to the other of source/drain regions
5
through contact hole
19
.
Capacitor
30
has a storage node
23
, a capacitor insulating layer
25
and a cell plate (an upper electrode)
27
. Storage node
23
is electrically connected to source/drain region
5
through contact hole
19
and extends on interlayer insulating layer
17
. Cell plate
27
is opposed to that portion of storage node
23
which extends over interlayer insulating layer
17
, with capacitor insulating layer
25
posed therebetween.
Especially, this memory cell structure is characterized in that storage node
23
penetrates bit line
15
to electrically connect with source/drain region
5
of MOS transistor
10
. That is, bit line
15
is provided with a through hole
15
a
, and contact hole
19
for a storage node contact passes through thorough hole
15
a.
Since the conventional semiconductor memory device has the above structure, it may be manufactured by the following method.
FIGS. 49-52
are schematic cross sectional views illustrating the steps of manufacturing the conventional semiconductor memory device. Referring first to
FIG. 49
, element-isolating insulating film
3
a
and p
+
channel stopper region
3
b
thereunder are formed to define an active region on a surface of p-type silicon substrate
1
. Gate electrode layer
9
having a predetermined shape is formed on p-type silicon substrate
1
with gate insulating layer
7
posed therebetween. The paired n-type source/drain regions
5
,
5
are formed such that that region on p-type silicon substrate
1
which is positioned below gate electrode layer
9
is sandwiched between source/drain regions
5
,
5
. Thus, MOS transistor
10
is provided that is formed of the paired n-type source/drain regions
5
,
5
, gate insulating layer
7
and gate electrode layer
9
.
Interlayer insulating layer
11
is formed to cover MOS transistor
10
. Contact hole
13
is formed in interlayer insulating layer
11
by typical photolithography and etching techniques. Bit line
15
is formed such that it electrically connects with one of the paired n-type source/drain regions
5
and extends on interlayer insulating layer
11
. Through hole
15
a
is formed in bit line
15
by the typical photolithography and etching techniques.
Referring to
FIG. 50
, interlayer insulating layer
17
is formed on interlayer insulating layer
11
to fill through hole
15
a
and to cover bit line
15
.
Referring to
FIG. 51
, a resist pattern
141
a
is formed on interlayer insulating layer
17
by the typical photolithography technique. Resist pattern
141
a
is used as a mask and anisotropic etching is performed. Thus, contact hole
19
is formed that passes through hole
15
a
in bit line
15
to reach the other of n-type source/drain regions
5
. Then, resist pattern
141
a
is removed.
Referring to
FIG. 52
, storage node
23
of the capacitor is formed such that it electrically connects with n-type source/drain region
5
through contact hole
19
and extends on interlayer insulating layer
17
.
Then capacitor insulating film
25
and cell plate
27
are formed and the conventional semiconductor memory device shown in
FIGS. 46-48
is completed.
In the conventional semiconductor memory device, it is not necessary to provide a storage node contact avoiding bit line
15
, since contact hole
19
penetrates bit line
15
, as shown in
FIGS. 46-48
. Therefore, increase in the size of a memory cell due to the necessity of avoiding bit line
15
can be prevented. In this respect, the structure of the conventional semiconductor memory device is advantageous to high integration.
For the conventional semiconductor memory device, however, after the formation of through hole
15
a
in bit line
15
, contact hole
19
is formed to pass through hole
15
a
. This causes short-circuit between storage node
23
and bit line
15
or gate electrode layer
9
due to misregistration of a mask. This problem will now be described in detail.
The center (represented by the chained line T—T) of a hole pattern
143
a
of resist pattern
141
a
shown in
FIG. 51
might be displaced to the right or left due to the misregistration of the mask.
FIG. 53
is a cross sectional view illustrating hole pattern
143
a
displaced to the right in the figure due to misregistration of the mask of resist pattern
141
a
in FIG.
51
. Referring to
FIG. 53
, if resist pattern
141
a
is used as a mask and the underlying layers are etched with hole pattern
143
a
displaced, bit line
15
might undesirably be exposed at the side wall of contact hole
19
. If storage node
23
of the capacitor is formed with bit line
15
exposed at contact hole
19
, storage node
23
and bit line
15
will short-circuited, as shown in FIG.
54
.
Furthermore, if hole pattern
143
a
is displaced due to the mask misregistration, gate electrode layer
9
can be exposed at the sidewall of contact hole
1

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