Method of fabricating trench for SOI merged logic DRAM

Details Method of fabricating trench for SOI merged logic DRAM Method of fabricating trench for SOI merged logic DRAM

1999-06-16

2001-05-15

Pham, Long (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S387000, C438S479000, C438S700000, C438S155000

Reexamination Certificate

active

06232170

ABSTRACT:

DESCRIPTION P 1. FIELD OF THE INVENTION
The present invention relates to semiconductor processing, and in particular to methods of manufacturing merged logic dynamic access memory (DRAM) devices on a silicon-on-insulator (SOI) wafer having a relatively thick buried oxide (BOX) region formed therein. Specifically, the various methods of the present invention provide merged logic DRAM devices wherein the deep trenches for the storage capacitor are etched into the SOI without etching through the BOX region present in the logic portion of the device. The methods of the present invention allow for fabricating high performance SOI merged logic DRAM devices.
2. Background of the Invention
In the field of semiconductor device manufacturing, merged logic DRAM devices are becoming increasingly important. This is so since the coupling of logic devices with DRAM cells provides a device which has all the benefits of DRAMs, but having the speed of conventional logic devices to improve bandwidth and performance.
Currently, one of the key problems in manufacturing merged logic DRAM devices is etching deep trenches (on the order of 6000 to 10,000 nm (6 to 10 microns) in the substrate) for the fabrication of storage capacitors. This difficulty is caused by the need to use a very thick hard mask such as SiO
2
as a masking material for reactive ion etching (RIE). The requirement of using a hard masking material for RIE has stretched current trench storage DRAM technologies to its limit.
Moreover, for high performance devices there is a trend in switching from using conventional bulk semiconductor wafers to silicon-on-insulator (SOI) wafers. In SOI wafers, a very thick buried oxide (BOX) region, on the order of about 800 to about 5000 Å, is typically present. This BOX region makes deep trench RIE even more difficult, if not impossible, due to hard mask consumption during the RIE process.
In view of the above drawbacks with manufacturing prior art merged logic DRAM devices, there is a continued need for developing new and improved methods of forming a deep trench storage capacitor in such structures wherein an SOI substrate having a BOX region is employed. Such methods must be capable of providing a deep trench in the SOI wafer without consumption of any BOX region that is present in the logic portion of the device.
SUMMARY OF THE INVENTION
One object of the present invention is to provide a method of manufacturing a merged logic DRAM device wherein the deep trench storage capacitor can be formed without having to etch through the buried oxide layer that is present in the logic portion of the SOI substrate.
Another object of the present invention is to provide a method of manufacturing high performance SOI merged logic DRAM devices.
A further object of the present invention is to provide a method which utilizes existing semiconductor processing technology to fabricate an SOI merged logic DRAM device.
These and other objects and advantages are obtained in the present invention by employing various processing schemes which are capable of etching deep trenches in the array portion of an SOI substrate without etching the thick BOX region in the logic portion of the SOI substrate. Specifically, the present invention provides methods for forming a merged logic DRAM device on an SOI wafer having a relatively thick BOX region, wherein a deep trench is etched into the SOI substrate without etching through the BOX layer present in the logic portion of the substrate.
In one method of the present invention, a high performance SOI merged logic DRAM device is formed using the following processing steps:
(a) providing an SOI substrate having a buried oxide layer formed therein, said SOI substrate further comprising selected areas for forming array devices and selected areas for forming logic devices;
(b) forming an insulator layer on a surface of said SOI substrate;
(c) forming a blockout photoresist pattern on said insulator layer over said selected logic device areas;
(d) etching said insulator layer so as to remove said insulator layer in said selected array device areas;
(e) etching the SOI substrate through said BOX layer in said selected array device areas;
(f) removing said patterned photoresist located over said selected logic device areas;
(g) forming an epitaxial silicon layer in the etched areas of said selected array device areas;
(h) forming a deep trench mask pattern over said selected array device areas; and
(i) etching a deep trench in said selected array device areas.
It is noted that the deep trench is formed in the selected array device areas without etching through the BOX layer in the logic device areas using conventional lithography and reactive ion etching (RIE). After conducting step (i), the array devices and logic devices can be formed using conventional methods well known in the art.
In a second method of the present invention, an SOI merged logic DRAM device is formed using the following processing steps:
(a) providing a silicon substrate having an insulator layer formed thereon, said substrate further comprising selected areas for forming array devices and selected areas for forming logic devices;
(b) forming a photoresist on said insulator layer;
(c) providing an opening in said photoresist and said insulator layer in areas wherein the array devices will be formed;
(d) etching a trench through said opening into said silicon substrate;
(e) removing said photoresist;
(f) filling said trench with a trench fill material;
(g) removing said insulator layer;
(h) forming a sacrificial oxide layer on said silicon substrate;
(i) forming a continuous BOX layer in said silicon substrate;
(j) providing a planarized structure; and
(k) removing said trench fill material and said BOX layer from said trench.
After conducting processing steps (a)-(k), the array and logic devices can be formed in the selective regions using conventional techniques well known to those skilled in the art.
In a third method of the present invention, an SOI merged logic DRAM device is fabricated as follows:
(a) providing a silicon substrate having an insulator layer formed thereon, said substrate further comprising selected areas for forming array devices and selected areas for forming logic devices;
(b) forming a photoresist on said insulator layer;
(c) providing an opening in said photoresist and said insulator layer in areas wherein the array devices will be formed;
(d) etching a trench through said opening into said silicon substrate;
(e) removing said photoresist;
(f) forming a sacrificial oxide layer on said silicon substrate and in the bottom of said trench;
(g) forming a discontinuous BOX layer in said substrate abutting said trench as well as a BOX region under said trench; and
(h) removing said sacrificial oxide layer on said silicon substrate and in said trench.
After conducting the above processing steps of the third method of the present invention, the array and logic devices can be formed in the selective regions using conventional techniques well known to those skilled in the art.


REFERENCES:
patent: 4916511 (1990-04-01), Douglas
patent: 5561073 (1996-10-01), Jerome et al.
patent: 5593912 (1997-01-01), Rajeevakumar
patent: 5627092 (1997-05-01), Alsmeier et al.
patent: 5732014 (1998-03-01), Forbes
patent: 5744386 (1998-04-01), Kenney
patent: 5759907 (1998-06-01), Assaderaghi et al.
patent: 5770484 (1998-06-01), Kleinhenz
patent: 5776808 (1998-07-01), Muller et al.
patent: 5792685 (1998-08-01), Hammerl et al.
patent: 5811283 (1998-09-01), Sun
R. Bashir, et al., “A Simple Process to Produce a High Quality Silicon Surface Prior to Selective Epitaxial Growth,” IEEE Electron Device Letters, vol. 16, No. 7, pp. 306-307 (1995).
J.M. Sherman, “Elimination of the Sidewall Defects in Selective Epitaxial Growth (SEG) of Silicon for a Dielectric Isolation Technology,”IEEE Electron Device Letters,vol. 17, No. 6, pp. 267-268 (1996).

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