Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1998-10-06
2001-02-20
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S264000, 43, C257S315000
Reexamination Certificate
active
06190967
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof. More specifically, the present invention relates to a semiconductor device which allows re-configuration of circuits freely by exchanging a program, and manufacturing method thereof.
2. Description of the Background Art
Recently, a semiconductor device called an FPGA (Field Programmable Gate Array) has been spread rapidly, which includes a gate array portion and a memory cell portion and allows re-configuration of circuitry freely by changing a program.
As a method for separating transistors in the gate array portion of the semiconductor device such as FPGA, use of an LOCOS (Local Oxidation of Silicon) oxide film is a first option.
FIG. 70
is a cross section showing a transistor separated by the conventional LOCOS oxide film. Referring to
FIG. 70
, an LOCOS oxide film
1002
is formed on a silicon substrate
1001
. A gate electrode
1080
of polycrystalline silicon is formed on silicon substrate
1001
with a gate oxide film
1007
interposed. An interlayer insulating film
1004
is formed to cover silicon substrate
1001
, LOCOS oxide film
1002
and gate electrode
1080
. LOCOS oxide film
1002
electrically separates an impurity regions positioned on the front side from an impurity region position on the back side with respect to the sheet.
FIG. 71
is an enlarged cross section of the portion surrounded by a circle A in FIG.
70
. Referring to
FIG. 71
, LOCOS oxide film
1002
expands in the step of oxidation. At this time, there is generated a strain in silicon substrate
1001
, resulting in a crystal defect near an interface between LOCOS oxide film
1002
and silicon substrate
1001
.
The crystal defect may be a cause of leak current generated in a depletion layer formed below the gate electrode
1080
when the transistor is in operation. This increases power consumption and causes malfunction of the transistor.
A method using an electrode for separation, that is, a so-called FS (Field Shield) separation method is a method of separation free of the above described problem.
FIG. 72
is a cross section showing transistors separated by using electrodes for separation. Referring to
FIG. 72
, electrodes
1040
for separation are formed on silicon substrate
1001
with an oxide film
1003
interposed. On silicon substrate
1001
, a gate electrode
1080
is formed with gate oxide film
1007
interposed. An interlayer insulating film
1004
is formed to cover separation electrode
1040
, silicon substrate
1001
and gate electrode
1080
. By applying a prescribed voltage to separation electrode
1040
, the potential of silicon substrate
1001
below separation electrode
1040
is fixed, so that the impurity region positioned in front is electrically separated from the impurity region positioned in the back direction of the sheet, whereby the transistors are separated. The voltage applied to separation electrode
1040
is 0V in an NMOS (Negative Metal Oxide Semiconductor) transistor, and it is Vcc (power supply voltage) in a PMOS (Positive Metal Oxide Semiconductor).
In the method of separation using such a separation electrode, the substrate experiences less strain as compared with separation by the LOCOS oxide film. As a result, a semiconductor device with smaller leak current can be obtained. Here, in the memory cell portion of the FPGA described above, an SRAM (Static Random Access Memory), an anti-fuse, a flash memory or the like is used. Especially in an FPGA using a non-volatile memory cell transistor such as a flash memory in the memory cell portion, it is possible to rewrite the stored contents a number of times, and further, FPGA consumes less power and the stored content is retained even when power is turned off. Therefore, such an FPGA is considered promising.
However, in a semiconductor device in which the gate array portion is separated by the separating portion using a separation electrode and in which a non-volatile memory cell transistor is used in the memory cell portion, it is necessary to form the gate electrode in the gate array portion, the separation electrode for the separating portion, and the floating gate electrode and the control gate electrode in the memory cell portion, which requires complicated steps of manufacture.
Further, high speed operation is required of a transistor in the gate array portion, and therefore the threshold value must be kept low. Meanwhile, for the non-volatile memory cell transistors in the memory cell portion and for the separating portion, the threshold value must be kept high in order to reduce leak current. Especially in the separating portion, when there is generated a leak current and it is conducted to the ON state, the gate array malfunctions. Therefore, the threshold value must be kept especially high. However, such problems have not been addressed in the conventional semiconductor devices.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor device which includes a plurality of field effect transistors separated by a separation electrode and a non-volatile memory cell transistor which can be manufactured through simple steps.
Another object of the present invention is to provide a semiconductor device including field effect transistors separated by a separation electrode and constituting a gate array, and a non-volatile memory cell transistor, which can be manufactured through simple steps.
A still further object of the present invention is to provide a semiconductor device including a plurality of field effect transistors separated by a separation electrode and a non-volatile memory cell transistor, which can be manufactured through simple steps, and which allows easy writing and erasure of the non-volatile memory cell transistor.
A still further object of the present invention is to provide a semiconductor device which includes field effect transistors separated by a separation electrode and non-volatile memory cell transistors separated by another separation electrode, which can be manufactured through simple steps.
A still further object of the present invention is to provide a semiconductor device in which threshold value for a non-volatile memory cell transistor is higher than that for a field effect transistor and the threshold value at a separating portion is not lower than the threshold value for the non-volatile memory cell transistor, that is, a semiconductor device which includes a non-volatile memory cell transistor, and field effect transistors capable of high speed operation and surely separated at the separating portion.
A still further object of the present invention is to provide a semiconductor device including field effect transistors separated by a separation electrode and capable of high speed operation, and a non-volatile memory cell transistor operable at a low voltage with small leakage of charges from the floating gate electrode.
A still further object of the present invention is to provide a semiconductor device in which a field effect transistor is surely electrically separated from a non-volatile memory cell transistor.
A still further object of the present invention is to provide a semiconductor device in which a floating gate electrode of a non-volatile memory cell transistor has the same gate length as the gate length of a control gate electrode.
The semiconductor device in accordance with the present invention includes a semiconductor substrate, field effect transistors, a non-volatile memory cell transistor and a first separating portion. The plurality of field effect transistors are formed on the semiconductor substrate. The non-volatile memory cell transistor is formed on the semiconductor substrate. The first separating portion includes a first separation electrode formed insulated on the semiconductor substrate. The first separating portion electrically separates the plurality of field effect transistors from each other. The non-volatile memory cell transistor includes a floating gate electrode
Maeda Shigenobu
Maegawa Shigeto
Yamaguchi Yasuo
Elms Richard
Luy Pho
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
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