Method of fabricating static random access memory cell with...

Details Method of fabricating static random access memory cell with... Method of fabricating static random access memory cell with...

2000-04-11

2001-05-29

Elms, Richard (Department: 2824)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S202000

Reexamination Certificate

active

06238962

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device, and more particularly, to a method of fabricating a static random access memory (SRAM) cell. Although the present invention is suitable for a wide scope of applications, it is particularly suitable for realizing the high packing density and cell stabilization of the static random access memory cell.
2. Discussion of the Related Art
Since a static random access memory (hereinafter referred to as SRAM) does not require refreshing of the memory and its operation timing is easily adjustable, it is capable of having the same access time and cycle time as a microcomputer. Further, the SRAM can be operated as fast as a random access memory (RAM). Accordingly, SRAMs are widely used in buffer memories of large size calculators, main memories in supercomputers, and control memories.
SRAMs using a flip-flop are classified into Enhancement/Depletion (E/D) type SRAMs, complementary metal oxide semiconductor (CMOS) type SRAMs, and high resistance-load type SRAMs.
A conventional SRAM cell will be explained with reference to the accompanying drawings.
FIG.
1
and
FIG. 2
are an equivalent circuit diagram and a layout of a conventional SRAM cell, respectively.
Referring to
FIG. 1
, first and second drive transistors TD
1
and TD
2
are based on a unit cell of a flip-flop, and gates of the first and second drive transistors TD
1
and TD
2
are connected to “B” and “A” points, respectively. As shown, in each of the unit cells, the first and second access transistors TA
1
and TA
2
are respectively connected to bit-lines B/L
1
and B/L
2
, and their gates are connected to the word-line W/L.
Referring to
FIG. 2
, a layout of a conventional SRAM cell has a complicated structure because active regions are formed having irregular shapes. That is, an SRAM cell includes active regions irregularly formed in a limited region, gate electrodes of first and second access transistors formed in predetermined portions of the active regions, and gate electrodes of first and second drive transistors. The gate electrode of the first access transistor and the gate electrode of the second drive transistor are connected to each other on a drain region of the first access transistor. Also, the gate electrode of the second access transistor and the gate electrode of the first drive transistor are connected to each other on a drain region of the second access transistor. The gate electrode of the second drive transistor is connected to the drain of the first drive transistor through a first contact hole. The gate electrode of the second drive transistor is connected to a load resistance R
1
through a second contact hole. At this time, the first and second contact holes are located in the same line.
Operations of the conventional SRAM will now be explained with reference to
FIG. 1
as follows.
When a high signal is applied to a word-line W/L, the first and second access transistors TA
1
and TA
2
are turned on, so that the unit cell is electrically connected to the bit-line. When the first drive transistor TD
1
is off and the second drive transistor TD
2
is on, the data of the bit-line B/L
2
is transmitted to a memory cell through the second access transistor TA
2
. In contrast, when the first drive transistor TD
1
is off, the bit-line B/L
1
has no path for current and is charged-up by the first access transistor TA
1
. In other words, when a high level data is written in the memory cell, a voltage larger than a threshold voltage is applied to the word-line so that the first and second access transistors TA
1
and TA
2
are turned on. The high level data is thus applied to an “A” point. Since the electric potential of the A point is a high level, a high signal is applied to the gate of the second drive transistor TD
2
connected to the A point, and the second drive transistor TD
2
is turned on. In contrast, a low level data of the bit-line B/L
2
is applied to a “B” point, so that the first drive transistor is turned off.
Subsequently, in reading data, the bit-lines B/L
1
and B/L
2
become equi-potentials and a voltage larger than the threshold voltage is applied to the word-line, thereby turning on the first and second access transistors TA
1
and TA
2
. Accordingly, when the data is the high level at the A point, the electric potential of the bit-line B/L
1
is increased. Conversely, when the data is the low level at the A point, the electric potential of the bit-line B/L
1
is decreased.
FIG. 3
is a cross-sectional view showing a structure of a conventional SRAM. The conventional SRAM includes a field oxide layer
42
to define first and second active regions on a first conductivity type semiconductor substrate
41
, a gate electrode
43
of an access transistor on the first active region, and a gate electrode
44
of a drive transistor spaced by a predetermined distance from the gate electrode
43
covering the field oxide layer
42
and on the second active region, source and drain impurity regions
46
and
46
a
having a second conductivity type in the substrate
41
at both sides of the gate electrode
44
of the access transistor, an insulating layer
47
having a contact hole exposing the gate electrode
44
of the drive transistor on the entire surface including the gate electrode
43
and
44
, a load resistance layer
50
electrically contacting the gate electrode
44
of the drive transistor over the insulating layer
47
, a ground line
48
between the load resistance layer
50
and the gate electrode
44
of the drive transistor insulated from the load resistance layer
50
and the gate electrode
44
of the drive transistor, and a bit-line
52
contacting a source impurity region of the second conductivity type through the contact hole.
A conventional method of fabricating an SRAM cell having the aforementioned structure will be explained with the accompanying drawings as illustrated in
FIGS. 4A
to
4
D.
Referring to
FIGS. 4A
, a first polysilicon layer is formed on the entire surface of a first conductivity type semiconductor substrate
41
having active regions defined by a field oxide layer
42
. POCl
3
is doped into the first polysilicon layer. Next, a photoresist layer (not shown) is coated on the first polysilicon layer to define gate electrode regions of an access transistor and a drive transistor. The first polysilicon layer is selectively removed by a photo-etching process to form gate electrodes
43
and
44
of an access transistor and of a drive transistor. Then, with the gate electrodes
43
and
44
serving as masks, impurity ions of the second conductivity type are lightly doped into the substrate
41
.
Subsequently, a first insulating layer is formed on the entire surface including the gate electrodes
43
and
44
and then is etched-back to form sidewalls
45
on both sides of the gate electrode
43
of the access transistor. With the sidewalls
45
serving as masks, impurity ions having the second conductivity type are heavily doped to form source and drain impurity regions
46
and
46
a
having a lightly doped drain (LDD) structure. In this process, the portion, which is the boundary of the active region and the gate electrode
44
of the drive transistor, indicated as “A” in
FIG. 4A
is formed by the diffusion of doped POCl
3
into the first polysilicon layer.
Referring to
FIG. 4B
, a second polysilicon layer
47
is then formed on the entire surface including the gate electrodes
43
and
44
, a second insulating layer
47
. Subsequently, a photoresist layer is coated on the second polysilicon layer to define a power-line. Next, the photoresist layer is patterned with a photo-etching process to form a ground line
48
.
Referring to
FIG. 4C
, a third insulating layer
49
is formed on the entire surface of the second insulating layer
47
including the ground-line
48
. Subsequently, the second and third insulating layers
47
and
49
are selectively removed to form a contact hole exposing the gate electrode
44
of the drive

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