Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-03-29
2001-05-22
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S305000, C438S306000
Reexamination Certificate
active
06235596
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 88103137, filed Mar. 2, 1999, the full disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
Field of the Invention
This invention relates to a method for manufacturing a semiconductor device. More particularly, the invention relates to a method for manufacturing a MOS (Metal Oxide Semiconductor) device with multiple threshold voltages in the semiconductor device.
Description of Related Art
The conventional transistor has only two kinds of status, which are “ON” and “OFF”. Therefore, the conventional transistor provided in a memory device can only be used for storing a data of a bit, which is either “0” or “1”. If there are N bits for storing, there must be an equivalent number of independent transistors to store these N bits data. The capacity for storing data per unit of volume in the memory device can not be efficiently increased as the semiconductor technique has an unexpected development.
For the above-described need, a MOS device with multiple voltages has been developed recently for using in the memory device. A conventional method for manufacturing these kinds of memory devices is forming a gate oxide layer with different thickness for a transistor in the memory device. The other conventional method is forming doped regions with different concentrations for a transistor in the memory device. These two conventional methods for forming a MOS device with multiple threshold voltages has the same feature, which extra masks are necessary for the multiple threshold voltages. The number of masks used in the manufacturing process is an index for the difficulty of the process. If more masks are necessary for a manufacturing process, it is difficult to control the reliability of the products and the reproduction of the pattern of the mask in the process. A choke point for manufacturing the MOS device with multiple threshold voltages is faced in the conventional methods.
SUMMARY OF THE INVENTION
The invention provides a method for manufacturing a MOS device with multiple threshold voltages, which additional masks are not necessary for the method, which can reduce the difficulty and the cost of the manufacturing process.
The invention provides a reliable and cost-reduced manufacturing method for MOS devices with multiple threshold voltages.
In accordance with the foregoing and other objectives of the invention, a method for manufacturing a MOS device with multiple threshold voltages is provided. The method comprises providing a substrate. A shallow trench isolation structure is formed in the substrate. The top surface of the shallow trench isolation structure is higher than surface of the substrate. An active region which is surrounded by the shallow trench isolation structure is defined in the substrate. A first process of ion implantation is performed on the substrate except a portion of the substrate under the shallow trench isolation structure. A first spacer is formed on the sidewall of a portion of the shallow trench isolation structure above the substrate in the active region. A second process of ion implantation is performed on the substrate except a portion of the substrate under the shallow trench isolation structure and the first spacer.
The method further comprises forming a second spacer on the sidewall of the first spacer in the active region; and performing a third process of ion implantation on the substrate except a portion of the substrate under the shallow trench isolation structure, the first spacer and the second spacer.
The number of the threshold voltages in the MOS device depend on the real demand. A process of forming a spacer and performing a ion implantation can be used for additional threshold voltage in the MOS device. Furthermore, the technique of forming spacers is well developed in the modern semiconductor-manufacturing field. That is, the width of the spacers can be easily controlled for forming threshold-voltage doped regions, which can be used for forming different threshold voltages. The concentration of the doped regions is also easily controlled for different values of the threshold voltages. Besides, additional masks are not necessary for this invention, which can reduce the difficulty and the cost of the manufacturing process. Therefore, the invention provides a reliable and cost-reduced manufacturing method for MOS devices with multiple threshold voltages.
REFERENCES:
patent: 5847428 (1998-12-01), Fulford, Jr. et al.
patent: 5950090 (1999-09-01), Chen et al.
Huang Jiawei
J.C. Patents
Le Dung A
Nelms David
United Microelectronics Corp.
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