Method of fabricating a split gate memory cell

Details Method of fabricating a split gate memory cell Method of fabricating a split gate memory cell

1999-12-14

2001-01-02

Booth, Richard (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

Utility Patent

active

06168995

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for fabricating a memory cell and more particularly a method for fabricating a split gate memory cell useful for low voltage operation.
2. Description of the Prior Art
As device technology scales down, doping concentrations in devices keep increasing. The resultant decrease in oxide/junction breakdown voltage makes it difficult to utilize high voltages required for the operation of non-volatile (NV) memory cells. Further, in the select gate of a split-gate memory cell itself, one needs relatively thicker gate oxides to prevent oxide breakdown. This makes it difficult to scale the Vt's of the select gate device and thus leads to poorer low voltage operation.
Scientists at Samsung Corp. have proposed the idea of a built-in charge pump for use in stacked gate cells (termed Boosted wordline cell) in an effort to address the aforementioned problems. The cells proposed by Samsung require the use of a triple poly structure. The present invention addresses the aforementioned problems through the use of a novel cell have a two-poly structure.
SUMMARY OF THE INVENTION
The present invention comprises a method of fabricating a novel split gate memory cell.
The novel split gate cell comprises a silicon substrate having a tunnel oxide layer on a portion of its surface and a first control gate and a floating gate electrode spaced from each other and preferably formed from the same material over the tunnel oxide. A dielectric layer overlies the first control gate and the floating gate electrodes, including the surface of the electrodes in the area between them. A second control gate, which is physically separated from the first control gate is provide over the dielectric layer and in the space between the first control gate and the floating gate. A highly doped region may be provided in the silicon substrate in the region under the separation of the first control gate and the floating gate. Source and drain regions are also provided in the substrate which may include adjacent halo implants.
The novel memory cell is fabricated by providing a tunnel oxide layer on the surface of a silicon substrate; forming a conductive layer over the tunnel oxide; forming a space in the conductive layer so as to provide a control gate and a floating gate electrode separated from each other but made from the same deposited or grown layer; forming a highly doped region in the substrate below the space between the aforementioned electrodes; forming a dielectric layer over the surfaces of the aforementioned electrodes; and forming a second control gate over the dielectric layer.


REFERENCES:
patent: 5049516 (1991-09-01), Arima
patent: 5273923 (1993-12-01), Chang et al.
patent: 5439838 (1995-08-01), Yang
patent: 5877523 (1999-03-01), Liang et al.
patent: 5920776 (1999-07-01), Fratin et al.

Affiliated with

Also associated with

Rating

Method of fabricating a split gate memory cell does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of fabricating a split gate memory cell, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of fabricating a split gate memory cell will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2553740