Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-02-04
2001-04-03
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S256000, C438S296000, C438S253000, C438S254000
Reexamination Certificate
active
06211012
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 89100262, filed Jan. 10, 2000.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device, and more particularly to a method of fabricating an ETOX flash memory.
2. Description of the Related Art
ETOX flash memory is a type of erasable programmable read only memory (EPROM) that also incorporates a thin tunnel oxide structure. It is therefore called “ETOX” (EPROM with Tunnel Oxide) flash.
According to a method of fabricating ETOX flash memory cell in the prior art, a plurality of parallel field oxide lines are formed in the substrate to serve as a device isolation structure. Stacked word lines having a tunneling oxide layer, a floating gate, an ONO (oxide-nitride-oxide) layer and a control gate are then formed on the substrate, wherein the stacked word lines are parallel to each other and perpendicular to the field oxide lines. A buried source line and drain region are formed on each side of the stacked word line by implanting ions in the substrate. A contact plug connected to a bit line is formed on the drain region. The buried source line is perpendicular to the field oxide line, and the bit line is parallel to the field oxide line.
Since the buried source line in the prior art crosses the field oxide line, the buried source line is curved and therefore has a varied distribution because of the field oxide line. However, the field oxide line limits the shrinkage of the ETOX flash memory, as the integration of the integrated circuit increases. Hence, shallow trench isolation (STI) lines substituted for the field oxide lines are employed to solve the problem. But, as shown in
FIG. 1
, while fabricating the buried source line
16
, ions
14
are generally implanted in a direction perpendicular to the silicon substrate
10
, an distribution of the doped ions follows the profile of the STI lines
12
. A very thin ion-doped layer
18
is formed next to the sidewalls of the STI lines
12
. Consequently, discontinuity and high resistance may occur somewhere along the source line
16
, and operation speed of the ETOX flash memory is therefore decreased..
SUMMARY OF THE INVENTION
The present invention therefore provides a method of fabricating ETOX flash memory. Self-aligned and low-resistance source lines are formed on a substrate to string each source region of the flash memory cells. The source line is employed as a substitute for the conventional buried source line, and the source line resistance can be reduced effectively. The operation speed of the ETOX flash memory is therefore increased.
The invention provides a method of fabricating an ETOX flash memory. The method of the invention comprises the following steps. A plurality of parallel device isolation lines, such as shallow trench isolation lines, is formed in a substrate. A plurality of parallel stacked word lines is formed on the substrate and in a direction perpendicular to the device isolation lines. A plurality of parallel source arrays and drain arrays are alternately positioned in the substrate between neighboring stacked word lines. Each source array has a plurality of source regions separately positioned between device isolation lines and each drain array also has a plurality of drain regions separately positioned between device isolation lines. A plurality of patterned first insulating layers is then formed, wherein each first insulating layer is on part of the device isolation lines between neighboring drain regions of one drain array. A plurality of source lines is formed on the source arrays, and a plurality of landing pads is formed on the drain regions at the same time. Each source line is electrically connected to the source regions of one source array. Each landing pad is electrically connected to a corresponding drain region. A second insulating layer is formed over the substrate. A plurality of contact plugs is formed in the second insulating layer, and a plurality of parallel bit lines running parallel to the device isolation lines is formed on the second insulating layer, wherein the contact plugs are electrically connected to the drain regions and bit lines.
According to the method of the invention, the flash memory is compact and small flash memory cells are made. Moreover, low-resistance source lines are formed on the source arrays to string the source region of each source array. Hence, the source lines can be made of low-resistance materials, and the implant dosage of the source region can be adjusted according to the device characteristic without affecting the source line resistance. In addition, landing pads are formed at the same time while forming the source line. The landing pads can reduce the aspect radio of the contact plugs, and thus decrease the etching difficulty of the contact windows while fabricating contact plugs. Furthermore, the source lines and landing pads are formed self-aligned and the fabricating process can be simplified.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.
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Chen Hwi-Huang
Hong Gary
Lee Robin
Huang Jiawei
J. C. Patents
Smith Matthew
United Microelectronics Corp.
Yevsikov V.
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