Semiconductor device having reduced polysilicon gate...

Details Semiconductor device having reduced polysilicon gate... Semiconductor device having reduced polysilicon gate...

1997-08-29

2001-03-20

Mulpuri, Savitri (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S303000, C438S305000, C438S585000, C438S595000

Reexamination Certificate

active

06204130

ABSTRACT:

FIELD OF THE INVENTION
The present invention is directed generally to semiconductor devices and, more particularly, to a semiconductor device having reduced polysilicon gate electrode width and method of manufacture thereof.
BACKGROUND OF THE INVENTION
Over the last few decades, the electronics industry has undergone a revolution by the use of semiconductor technology to fabricate small, highly integrated electronic devices. The most common semiconductor technology presently used is silicon-based. A large variety of semiconductor devices have been manufactured having various applicability and numerous disciplines. One such silicon-based semiconductor device is a metal-oxide-semiconductor (MOS) transistor.
The principal elements of a typical MOS semiconductor device are illustrated in FIG.
1
. The device generally includes a gate electrode
101
, which acts as a conductor, to which an input signal is typically applied via a gate terminal (not shown). Heavily doped source
103
and drain
105
regions are formed in a semiconductor substrate
107
and are respectively connected to source and drain terminals (not shown). A channel region
109
is formed in the semiconductor substrate
107
beneath the gate electrode
101
and separates the source
103
and drain
105
regions. The channel is typically lightly doped with a dopant type opposite to that of the source
103
and drain
105
regions. The gate electrode
101
is physically separated from the semiconductor substrate
107
by a gate insulating layer
111
, typically an oxide layer such as SiO
2
. The insulating layer
111
is provided to prevent current from flowing between the gate electrode
101
and the semiconductor source region
103
, drain region
105
or channel region
109
.
In operation, an output voltage is typically developed between the source and drain terminals. When an input voltage is applied to the gate electrode
101
, a transverse electric field is set up in the channel region
109
. By varying the transverse electric field, it is possible to modulate the conductance of the channel region
109
between the source region
103
and drain region
105
. In this manner an electric field controls the current flow through the channel region
109
. This type of device is commonly referred to as a MOS field-effect-transistors (MOSFET).
Semiconductor devices, like the one described above, are used in large numbers to construct most modern electronic devices. In order to increase the capability of such electronic devices, it is necessary to integrate even larger numbers of such devices into a single silicon wafer. As the semiconductor devices are scaled down (i.e., made smaller) in order to form a larger number of devices on a given surface area, the structure of the devices and fabrication techniques used to make such devices must be altered.
One important step in the manufacture of MOS devices is the fabrication of the gate electrode. The gate electrode is typically formed by depositing a layer of polysilicon and selectively removing portions of the polysilicon layer, using well-known photolithography and etching techniques. These conventional techniques for forming gate electrodes however impose limitations on the minimum width of the gate electrode. The resolution of the photolithography process, in particular, imposes limitations on the minimum width of the gate electrode. As the thresholds for minimum thickness are reached, the ability to further scale down the semiconductor devices is hindered.
SUMMARY OF THE INVENTION
Generally, the present invention relates to a semiconductor device having a reduced polysilicon gate electrode width and a process for manufacturing such a device. Consistent with the present invention a semiconductor device is formed by forming an insulating film selective to an oxide etchant over a substrate. At least one polysilicon block is formed over the insulating film. The polysilicon block is then oxidized to form an oxide layer on exposed surfaces of the polysilicon block and reduce the width of the polysilicon block. The oxide layer is then removed to form a gate electrode from the remaining portion of the polysilicon block. In this manner, the initial width of a polysilicon block can be reduced to form a narrow gate electrode. This, for example, allows the formation of gate electrodes having widths smaller than the minimum resolution of current etching techniques.
A semiconductor device consistent with an embodiment of the invention includes a substrate and an insulating film selective to an oxide etchant disposed over the substrate. At least one polysilicon gate electrode is disposed over the insulating film. In accordance with one aspect of the invention, the polysilicon gate has a width of about 0.10 microns or less. In accordance with another aspect, the insulating layer selective to oxide etchant is formed from a high permittivity material, such as a barium strontium titanate oxide.
The above summary of the present invention is not intended to describe each illustrated embodiment or every implementation of the present invention. The figures and the detailed description which follow more particularly exemplify these embodiments.


REFERENCES:
patent: 4869781 (1989-09-01), Euen et al.
patent: 5476802 (1995-12-01), Yamazaki et al.
patent: 5650649 (1997-07-01), Tsukiji
patent: 5858843 (1999-01-01), Doyle et al.
patent: 5891809 (1999-04-01), Chau et al.

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