Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1994-04-18
2001-04-24
Le, Dieu-Minh T. (Department: 2184)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S726000
Reexamination Certificate
active
06223312
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a test-facilitating circuit for information processing circuits mainly comprising a microinstruction control unit, and particularly to a test-facilitating circuit which is useful for fault diagnosis and failure analysis.
2. Description of the Prior Art
There is self-test technology in the test-facilitating technology for LSI. A self-test is constructed based on signature analysis in which a test-data generating circuit, such as a linear feed-back shift register (LFSR), successively supplies test data to a circuit block to be tested in accordance with a start instruction from a suitable external system, and the output from the circuit block is contained in a signature compression circuit comprising an LFSR, thereafter the output is subjected to a signature compression process. Then, such a series of operations is finished, and the test result (signature) subjected to the signature compression is compared with an expected value which is previously prepared, so as to judge whether or not the object to be tested is a conforming article.
According to such a self-test mechanism, it becomes possible to discriminate whether or not a circuit block to be tested is faulty by comparing the test result and an expected value only once. Thus, the time for which a generally expensive LSI tester should be used can be greatly reduced. However, in this case, since the test procedure can not be observed from the outside, even when a discrepancy between the test result and an expected value is found after the test, it is impossible to recognize from the outside when and how it was generated.
For example, as a microprocessor of CISC (Complex Instruction Set Computer) type to which such a self-test mechanism is applied, there is a device with a construction as shown in FIG.
1
.
In
FIG. 1
, a plurality of circuit blocks
4
are mutually connected to one another through an internal bus
1
, and a &mgr; ROM
2
contains microprograms for a self-test consisting of microinstructions in its microprogram containing area for self-test. Further, a microinstruction decoder
3
decodes the microinstruction contained in the &mgr; ROM
2
, so as to produce control signals for controlling the respective circuit blocks
4
. Likewise, a test-data-generating circuit
5
and a signature compression circuit
6
are connected to the internal bus
1
and are respectively controlled by a control signal produced by decoding a microinstruction, so as to carry out self-test on the circuit blocks
4
.
As stated above, by making it possible to control the constructional elements necessary for the self-test under a microinstruction in the same control manner as in the circuit blocks to be tested, it becomes possible to reduce the overhead required for the test and to carry out the self-test on such plurality of circuit blocks in series.
In actual implementation, each circuit block is basically tested based on a microinstruction used for normal operation. However, since such a microinstruction for normal operation is generally constructed so as to use only limited functions of each circuit block in one step, the test is not carried out most efficiently. Therefore, a great many steps must be required for such a test microprogram and it becomes very difficult to contain the whole body of the test microprograms in the test microprogram containment area of the &mgr; ROM
2
. This problem has great influence particularly on recent CISC type microprocessors in which a plurality of high-function circuit blocks are contained. Thus, in order to solve this problem, there is proposed a construction as shown in
FIG. 2
, in which a plurality of multiplexers
26
(MUX 1, MUX 2, MUX 3) are disposed between a &mgr; ROM
2
and a microinstruction register
8
so as to select a counter
22
for carrying out count operation under a microloop instruction or the like in place of the &mgr; ROM
2
in accordance with a select signal which is contained in a self-test-control-information-containing ROM
23
and transferred through a register
25
. Moreover, in such a construction, a test microprogram for each circuit block is coded into such a form as to use the microloop instruction, and the whole body of self-test is controlled by a self-test control circuit
21
. As a result, it becomes possible to supply a plurality of test microinstructions to corresponding circuit blocks to be tested by one step of the test microprogram in the &mgr; ROM. Accordingly, the number of steps of the test microprogram to be contained in the &mgr; ROM can be greatly reduced into a range corresponding to the practical use. The increase of hardware required for such an arrangement is not so large. Thus, since the microinstruction control self-test has many merits as described above, it can be sufficiently applied to a large scale microprocessor.
On the other hand, in production of large scale LSI, reduction of the development term becomes an important problem in the competition of the industry. However, it is too time-consuming for competition to take a procedure of developing and evaluating respective functional blocks, then incorporating these functional blocks in a large scale LSI which is a true object of the development. Therefore, it is necessary to develop the whole body of the LSI from the first stage. To this end, the respective functional blocks should be efficiently evaluated almost independently in the incorporated state in such an LSI. Accordingly, the test-facilitating technology for efficiently carrying out fault diagnosis and failure analysis on each circuit block in a large scale LSI becomes important.
As a microprocessor for efficiently carrying out such fault diagnosis and failure analysis on each circuit block controlled under a microinstruction there is, for example, a construction as shown in FIG.
3
.
In the construction of the same drawing, for initial setting, a microinstruction including an instruction for providing operation of a circuit block
7
to be tested for fault diagnosis is inputted in a scanning manner to a microinstruction register
8
comprising a scan chain. At the same time, information for selecting an interface circuit (or interface element)
10
which serves as an interface between a circuit block to be used in the fault diagnosis and an internal bus
9
is inputted in a scanning manner to a scan chain
11
for fault diagnosis.
Thereafter, the inputted information is fixed, and a series of operations, comprising supply of test data to the circuit block
7
from a data pin
12
; containment of operation of the circuit block
7
to be subjected to the diagnosis in accordance with a control signal obtained by decoding the microinstruction inputted to the microinstruction register
8
by means of a microinstruction decoder
13
and the result thereof; and reading of the contained data to the outside from the data pin
12
or an address pin
14
. This is carried out in accordance with a control signal generated at a TGEN circuit
15
.
According to such a series of operations, since suitable test data which are necessary for the fault diagnosis and failure analysis can be supplied to a circuit to be tested, and further since the test procedure can be observed from the outside, it becomes possible to efficiently carry out effective and sufficient fault diagnosis and failure analysis.
Accordingly, such a self-test method is extremely effective for carrying out a shipping test on the related articles with efficiency. However, the method is not yet satisfactory for efficiently carrying out the fault diagnosis and failure analysis.
Namely, in such a self-test, since the test result is judged based on data (signature) processed by signature compression as stated above, only a few pieces of information can be obtained from the test procedure. Moreover, in order to suppress the cost increase to be caused by increasing the chip area, it is necessary to minimize the area occupied by the testing circuit. Therefor, it is very difficult to incorporate into th
Foley & Lardner
Kabushiki Kaisha Toshiba
Le Dieu-Minh T.
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