Static information storage and retrieval – Interconnection arrangements
Reexamination Certificate
2000-04-06
2001-03-20
Nelms, David (Department: 2818)
Static information storage and retrieval
Interconnection arrangements
C365S230030
Reexamination Certificate
active
06205045
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device and, more particularly, to its cell array layout.
A semiconductor device is manufactured by forming a number of chips on a wafer by lithography. In this process, the chip area determines the number of chips available from one wafer. That is, the cost of the semiconductor memory device largely depends on the chip area. Especially, most of a semiconductor memory device is occupied by a memory cell array, and its decoders and peripheral circuits. Efficient layout of the memory cell array is the most important factor in determining the manufacturing cost of the memory.
Conventionally, the wiring of the memory is formed by one metal interconnection layer and one or several polysilicon interconnection layers. Therefore, the arrangement and interconnections of the core portion including memory cells and decoders are optimized on the assumption of the single metal layer. In recent years, two or more metal interconnection layers have come to be used even in a memory. However, the arrangement and interconnections of the core portion remain almost the same as those of the conventional structure using one metal layer, so the manufacturing cost of the memory has not lowered significantly. For this reason, demand has arisen for reducing the layout area of the core portion by using a multilevel metal interconnection independently of the conventional layout.
The layout of a core unit using a single metal interconnection and that using a multilevel metal interconnection will be described below while exemplifying a conventional nonvolatile semiconductor memory device, e.g., a flash EEPROM (Electrically Erasable Programmable ROM).
FIG. 9
shows the schematic arrangement of the core portion using a single metal interconnection. In
FIG. 9
, the core portion of the nonvolatile semiconductor memory device comprises a memory cell array
90
a,
a row decoder
90
b,
a Y selector
90
c,
a reset transistor
90
d,
a write transistor
90
e,
a source decoder SOD (L/D: Load/Driver)
90
f,
an SOD (CONT: control)
90
g,
and a block decoder BLD
90
h.
The memory cell array
90
a
comprises, e.g., NOR EEPROM cells. The row decoder
90
b
selects the word lines of desired memory cells. The Y selector
90
c
selects bit lines in accordance with a column selection signal supplied from a column decoder (not shown). The reset transistor
90
d
resets the bit lines to the ground potential in the standby state or upon completing the program. The write transistor
90
e
applies a high voltage to the bit lines of desired memory cells in a write. The source decoder SOD (L/D)
90
f
applies a source potential to the memory cells through a source line SL. The SOD (CONT)
90
g
controls the source decoder SOD (L/D). The block decoder BLD
90
h
selects a desired cell array block.
In the case of the single metal interconnection, these circuits has configurations as shown in FIG.
10
.
FIG. 10
shows a plurality of cell array blocks, and the same reference numerals as in
FIG. 9
denote the same parts in FIG.
10
. In this case, a data line
100
and a control signal line
101
of the write transistors (write Tr)
90
e
constituted by a plurality of signals are shared, so two cell arrays
90
a
are laid out symmetrically about the data line
100
and the control signal line
101
.
The Y selector
90
c
connected to the data line
100
and the write transistor
90
e
are inserted between the memory cell array
90
a,
on the one hand, and the data line
100
and control signal line
101
, on the other hand. When the Y selector
90
c
and the write transistor
90
e
are located at the central portion of the chip, the remaining signal lines and-cell source lines can hardly be arranged at the central portion by the single metal interconnection. Especially, since the source decoder (SOD (L/D))
90
f
applies the source potential to the cells, this interconnection must have a low resistance. Inevitably, the source decoders
90
f
and
90
g
are disposed on the opposite side of the Y selector
90
c
with respect to the cell array
90
a.
The reset transistor (reset Tr)
90
d
is also located on the upper or lower side of the cell array
90
a
in
FIG. 10
in consideration of easy arrangement of signal and ground (GND) interconnections.
The layout of the core portion using the conventional multilevel metal interconnection will be described next with reference to FIG.
11
.
In case of the multilevel metal interconnection, to lower the resistance of the word lines in the core portion, the block is divided. For this purpose, a double word line scheme is used.
For example, 8 to 16 word lines are selected by a row global decoder (RGD)
111
a.
The output from the row global decoder
111
a
is connected to a second level metal interconnection (
2
Al)
111
c
and formed on the cell array. Each block has a row local decoder (RLD)
111
b
having a plurality of NAND circuits. The row local decoder (RLD)
111
b
selects one word line WL in accordance with the output signal from a row partial decoder (RPD) hid through-the first level metal interconnection (
1
Al) and the output signal from the row global decoder
111
a.
The Y selector, the reset transistor, the write transistor, the source decoder SOD (L/D), the SOD (CONT), and the block decoder BLD are located on the upper or lower side of the cell array in
FIG. 11
, as in the above-described core portion using the first level metal interconnection (
1
Al).
The address signal and control signal lines of each circuit are arranged on each circuit block using the second level metal interconnection to reduce the layout area.
When the circuit blocks are laid out in the periphery of the cell array, the space cannot be efficiently used because of the following problems.
(1) Since the circuit blocks and cell array are symmetrical about the data line, power supply interconnections including a ground interconnection GND and a power supply interconnection Vdd must be formed on both the upper and lower sides of the cell array, resulting in an increase in layout area.
(2) Since the circuit blocks are arranged on the upper and lower sides of the cell array, wiring for an address and control signal common to a plurality of circuit blocks must be formed on both upper and lower sides of the cell array, resulting in an increase in layout area.
(3) Since the circuit blocks are present on the upper and lower sides of the cell array, even substrate and well potential circuits common to a plurality of circuit blocks must be laid out on both the upper and lower sides of the cell array, resulting in an increase in wasteful layout area at the boundary between the substrate and well.
The prior art and its problems in layout of a core portion having blocks with irregular shapes and sizes and the layout of peripheral circuits will be described while exemplifying a nonvolatile semiconductor memory device, e.g., a flash EEPROM.
The memory cell array of the flash EEPROM is broken up into several units (blocks), and data is erased in units of blocks. The flash EEPROM also has a function of enabling or inhibiting writes/erases in/from cells in units of blocks. Normally, the blocks are formed by regularly dividing the cell array. For example, an 8 Mbit cell array is divided into 16 512-Kbit (64 KB) blocks.
The cell array is sometimes irregularly divided to form blocks. For example, an 8 Mbit cell array is broken up into 15×512 Kbit (64 KB)+1×256 Kbit (32 KB)+1×128 Kbit (16 KB)+2×64 Kbit (8 KB) blocks. In this case, the larger number of 512 Kbit (64 KB) blocks are called regular blocks, and the remaining 64 to 256 Kbit blocks are called irregular blocks. The user can write, e.g., fixed data of a peripheral device in this irregular block in accordance with the application purpose.
The cell array having irregular blocks has some unsolved problems of layout, unlike the completely regularly divided cell array.
FIGS. 12 and 13
show the schematic arrangement of a cell array having regular blocks
Atsumi Shigeru
Kuriyama Masao
Banner & Witcoff , Ltd.
Kabushiki Kaisha Toshiba
Nelms David
Tran M.
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