Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-10-09
2001-04-17
Hardy, David (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S372000
Reexamination Certificate
active
06218699
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention lies in the semiconductor field. More specifically, the invention relates to a semiconductor component with a first doped zone of a second conductivity type disposed in a semiconductor substrate of the first conductivity type, and a channel zone in the semiconductor substrate disposed adjacent to the first doped zone.
In integrated semiconductor circuits, bipolar transistors are usually used for current amplification. Because they have a plurality of doped zones each with their own terminal, the space required is relatively great.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a semiconductor component with adjustable current amplification based on a tunnel current controlled avalanche breakdown, which overcomes the above-mentioned disadvantages of the heretofore-known devices and methods of this general type and which allows very high current amplification while requiring little space.
With the foregoing and other objects in view there is provided, in accordance with the invention, a semiconductor component, comprising:
a semiconductor substrate of a first conductivity type;
a first doped zone of a second conductivity type disposed in the semiconductor substrate, the first doped zone having a surface, a peripheral region, and a terminal;
a channel zone of the first conductivity type disposed in the semiconductor substrate adjacent the first doped zone, the channel zone having a surface and a terminal;
a tunnel dielectric partly covering the surface of the first doped zone;
a gate dielectric covering the surface of the channel zone and the peripheral region of the first doped zone;
an insulation layer disposed on the peripheral region and being formed at least in part by the gate dielectric, the insulation layer having a greater layer thickness than the tunnel dielectric;
a tunnel gate electrode on the tunnel dielectric; and
a channel gate electrode on the gate dielectric;
wherein the first doped zone is connectible to a first potential and the channel zone is connectible to a second potential, such that a current flows between the first doped zone and the channel zone that is amplified relative to a current flowing through the tunnel dielectric by a given amplification factor, and wherein the given amplification factor is adjustable by a parameter selected from the group consisting of a thickness of the tunnel dielectric, a thickness of the gate dielectric, a thickness of the insulation layer, a dopant concentration of the first doped zone, a dopant concentration of the channel zone, and a size of the peripheral region.
In other words, the invention involves a semiconductor component that is based on a tunnel-current-controlled avalanche breakdown. The component has a first doped zone of a second conductivity type in a semiconductor substrate of a first conductivity type. A zone in the semiconductor substrate adjacent the first doped zone acts as a channel zone. The first doped zone is partly covered by a thin tunnel dielectric, and both the channel zone and a predetermined peripheral region of the first doped zone, which region adjoins the channel zone, are covered by a gate dielectric. A tunnel gate electrode is disposed on the tunnel dielectric, and a channel gate electrode is disposed on the gate dielectric. The channel gate electrode accordingly overlaps the predetermined peripheral region of the first doped zone. Both the first doped zone and the channel zone are connectable.
In accordance with an added feature of the invention, the gate dielectric is thicker than the tunnel dielectric. If a component with especially high current amplification is to be made, then both dielectrics can have the same thickness. In the embodiment with a common gate electrode, this can mean that a potential barrier, of the kind described in detail hereinafter, will not occur.
In accordance with an additional feature of the invention, the tunnel gate electrode and/or the channel gate electrode has a gate terminal.
In accordance with another feature of the invention, the tunnel gate electrode and the channel gate electrode are conductively connected to one another to form a common gate electrode.
In accordance with a further feature of the invention, the first conductivity type is a p conductivity type and the second conductivity type is an n conductivity type. In other words, the semiconductor substrate comprises p-conductive silicon and has a p
+
-doped zone as a terminal for the channel zone. The first doped zone is n-doped and is connectable via a further n
+
-doped zone.
In accordance with again a further feature of the invention, the first potential is a positive potential applied to the first doped zone, a non-positive potential is applied to the common gate via the gate terminal, and the semiconductor substrate is at ground potential.
In accordance with again an added feature of the invention, the parameters thickness of the tunnel dielectric, thickness of the gate dielectric, and size of the peripheral region of the first doped zone are selected such that at predetermined potentials electrons tunneling through the tunnel dielectric generate an avalanche breakdown to the channel zone.
In accordance with again another feature of the invention, there is provided a control gate disposed above and insulated from the common gate.
In accordance with again a further feature of the invention, a highly doped zone of the first conductivity type is formed in the semiconductor substrate for connecting the channel zone. Further, there is provided a highly doped zone of the second conductivity type in the semiconductor substrate for connecting the first doped zone.
The tunnel gate electrode and the channel gate electrode can be conductively connected to one another and form a common gate electrode, which can be made from the same conducting layer. The common gate can be connectible from outside to a voltage U
G
, but it can also be a so-called floating gate, similar to that of an EPROM. In the latter case, a control gate above the common gate is preferably provided. If the tunnel gate electrode and the channel gate electrode are insulated from one another, they can be connected to different potentials.
With the above and other objects in view there is also provided, in accordance with the invention, a method of producing a semiconductor component as described above: The production method incorporates the following steps:
forming a gate dielectric on a semiconductor substrate of a first conductivity type;
applying a photoresist mask to the gate dielectric, wherein the mask is formed with an opening defining a region of a tunnel dielectric to be produced;
producing a first doped zone of a second conductivity type below the opening by implanting through the gate dielectric;
removing the gate dielectric from the surface of the first doped zone except for a peripheral region of the first doped zone;
removing the remaining photoresist mask;
forming a tunnel dielectric on the exposed semiconductor substrate surface;
producing a tunnel gate electrode on the tunnel dielectric and a channel gate electrode on a predetermined portion of the gate dielectric; and
forming a terminal for a channel zone adjacent the first doped zone and forming a terminal for the semiconductor substrate.
In accordance with a concomitant feature of the invention, the gate dielectric is removed in self-adjusted fashion with respect to the first doped zone. This is effected with the photoresist mask used in the implanting step.
The component can be produced simply and requires little space. Producing the tunnel dielectric in self-adjusted form with respect to the first doped zone is especially advantageous, because by this provision the electrical properties of the component can be adjusted more precisely, and the space requirement is reduced.
Other features which are considered as characteristic for the invention are set forth in the appended claim.
Although the invention is illustrated and described herein as embodied in a
Greenberg Laurence A.
Hardy David
Infineon - Technologies AG
Lerner Herbert L.
Stemer Werner H.
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