Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1998-05-14
2001-07-17
Trinh, Michael (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S596000
Reexamination Certificate
active
06261903
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to the manufacture of semiconductor integrated circuits. More particularly, the invention is illustrated with regard to memory cell structures for a flash memory cell or flash E
2
PROM or EPROM cell, but it will be recognized that the invention has a wider range of applicability. Merely by way of example, the present invention can be applied to a variety of embedded memory cell structures such as microprocessors (“MICROs”), microcontrollers, application specific integrated circuits (“ASICs”), and the like.
A variety of memory devices have been proposed or used in industry. An example of such a memory device is an erasable programmable read-only memory (“EPROM”) device. The EPROM device is both readable and erasable, i.e., programmable. In particular, an EPROM is implemented using a floating gate field effect transistor, which has binary states. That is, a binary state is represented by the presence of absence of charge on the floating gate. The charge is generally sufficient to prevent conduction even when a normal high signal is applied to the gate of the EPROM transistor.
Numerous varieties of EPROMs are available. In the traditional and most basic form, EPROMs are programmed electrically and erased by exposure to ultraviolet light. These EPROMs are commonly referred to as ultraviolet erasable programmable read-only memories (“UVEPROM”s). UVEPROMs can be programmed by running a high current between a drain and a source of the UVEPROM transistor while applying a positive potential to the gate. The positive potential on the gate attracts energetic (i.e., hot) electrons from the drain-to-source current, where the electrons jump or inject into the floating gate and become trapped on the floating gate.
Another form of EPROM is the electrically erasable programmable read-only memory (“EEPROM” or “E
2
PROM”). EEPROMs are often programmed and erased electrically by way of a phenomenon known as Fowler-Nordheim tunneling. Still another form of EPROM is a “Flash EPROM,” which is programmed using hot electrons and erased using the Fowler-Nordheim tunneling phenomenon. Flash EPROMs can be erased in a “flash” or bulk mode in which all cells in an array or a portion of an array can be erased simultaneously using Fowler-Nordheim tunneling, and are commonly called “Flash cells” or “Flash devices.”
A limitation with the flash memory cell is high voltage is often required to program the device. In some conventional devices, the high voltage can be up to double the amount of voltage needed to operate the device. As device size becomes smaller, high voltage is often detrimental to the operation of the device, as well as its reliability. In particular, high voltages often require a high voltage supply, which uses a more efficient voltage pump. This voltage pump generally requires a thicker oxide for the transistor device, which is often more difficult to make accurately. Additionally, higher voltages often lead to reliability and quality problems. These and other limitations exist in conventional flash memory devices. From the above it is seen that a flash memory cell structure that is easy to fabricate, cost effective, and reliable is often desired.
From the above, it is seen that an improved isolation structure for an integrated circuit device is highly desirable.
SUMMARY OF THE INVENTION
The present invention provides a technique, including a method and device, for an improved flash memory device. In particular, the present invention provides a novel gate structure, including floating and control gates, for a flash memory cell.
In a specific embodiment, the present invention provides a novel integrated circuit device, which has a flash memory cell. The flash memory cell has a tunnel dielectric layer overlying a surface of a semiconductor substrate. A floating gate layer is defined overlying the tunnel dielectric layer. The gate layer has an edge defined thereon, where a sidewall spacer extends along and on the edge. The sidewall spacer includes a first portion defined adjacent to the edge and a second portion extending from the first portion to a region substantially outside the edge. The combination of the sidewall spacer and the gate layer provide a novel surface for increasing gate coupling ratio (“GCR”).
In an alternative embodiment, the present invention provides a novel method for forming an integrated circuit device that includes a flash memory cell. The method includes steps of forming a tunnel dielectric layer overlying a surface of a semiconductor substrate, and forming a floating gate layer overlying the tunnel dielectric layer. The gate layer has an edge defined thereon. The method also includes a step of forming a sidewall spacer extending along and on the edge. The sidewall spacer has a first portion defined adjacent to the edge and a second portion extending from the first portion to a region substantially outside the edge. Among other features, the combination of the sidewall spacer and the gate layer provides a novel surface structure for increasing GCR.
Numerous benefits are achieved in one or more embodiments of the present invention over conventional techniques. For example, the present invention provides a relatively simple structure to increase a gate coupling ratio of a flash memory device in an embodiment. The increased gate coupling ratio leads to lower voltages needed to program the device. Additionally, the present invention uses a simple technique for manufacturing the novel flash memory cell. This technique relies on conventional technology including sidewall spacers. These and other benefits are described throughout the present specification, and more particularly below.
The present invention achieves these benefits in the context of known process technology. A further understanding of the nature and advantages of the present invention, however, may be realized by reference to the latter portions of the specification and attached drawings.
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Sung Kuo-Tung
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Townsend and Townsend / and Crew LLP
Trinh Michael
Vockrodt Jeff
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