Method of manufacturing salicide layer

Details Method of manufacturing salicide layer Method of manufacturing salicide layer

1999-07-01

2001-01-23

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S279000, C438S286000, C438S592000

Reexamination Certificate

active

06177319

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 88100647, filed Jan. 16, 1999, the full disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device. In particular, the present invention relates to a method of manufacturing a salicide layer in an embedded structure.
2. Description of the Related Art
Typically, logic devices and memory devices are formed on the different wafers. In order to increase the efficiency of the integrated circuits (ICs), an embedded structure comprising a memory device region and a logic circuit region has been developed. The embedded structure has the benefit of decreasing production cost as well as improving the functional capacity of the devices. Integration improves functionality by lowering the time delay for sending signals from a memory device in one part of a semiconductor chip to a logic device in another part of another semiconductor chip. In addition, by putting memory and logic devices together on a semiconductor chip, cost of production is lowered because they can share most common fabrication procedures.
The most common embedded structure is an embedded dynamic random access memory (DRAM). The embedded DRAM comprises a logic circuit, a transfer field effect transistor (transfer FET) and a capacitor electrically coupled to the transfer FET. The transfer FET is used as a selectively coupled switch between a bottom electrode of the capacitor and a bit line. Hence, the data can be read from or stored in the capacitor.
FIGS. 1A through 1D
are schematic, cross-sectional views of the conventional process for manufacturing a salicide layer in an embedded structure.
As shown in
FIG. 1A
, a substrate
100
having a memory region
102
a
and a logic circuit region
102
b,
which are isolated by an isolation region (not shown), is provided. A gate oxide layer
104
is formed over the substrate
100
. A polysilicon layer
106
and a silicide layer
108
are formed over the substrate
100
in sequence.
As shown in
FIG. 1B
, the silicide layer
108
, the polysilicon layer
106
and the gate oxide layer
104
are patterned to form gate oxide layers
104
a
and
104
b,
polysilicon layers
106
a
and
106
b
and silicide layers
108
a
and
108
b.
The gate oxide layer
104
a,
the polysilicon layer
106
a
and the silicide layer
108
a
together form a gate structure
110
a.
The gate oxide layer
104
b,
the polysilicon layer
106
b
and the silicide layer
108
b
together form a gate structure
110
b.
Source/drain regions
112
a
and
112
b
are formed in the substrate
100
by an implantation step and spacers
114
a
and
114
b
are respectively formed on the sidewalls of the gate structures
110
a
and
110
b.
As shown in
FIG. 1C
, an oxide layer
116
is formed to cover the memory region
102
a.
A titanium layer
118
is formed over the substrate
100
.
As shown in
FIG. 1D
, a portion of the titanium layer
118
over the source/drain region
112
b
is silicified by a thermal process to form a salicide layer
120
. The remaining titanium layer
118
and the oxide layer
116
(as shown in
FIG. 1C
) are removed.
Conventionally, the silicide layers
108
a
and
108
b
formed on the polysilicon layers
106
a
and
106
b
are used to decrease the resistance of the gate structure. However, the implantation step used to form the source/drain regions
112
a
and
112
b
affects the structure of the silicide layers
108
a
and
108
b
while the implantation step is performed. Additionally, the annealing step used to uniform the ion distribution in the source/drain regions
112
a
and
112
b
and to decrease the stress of the source/drain regions
112
a
and
112
b
also affects the structure of the silicide layers
108
a
and
108
b.
Therefore, the resistance of the gate structure cannot be efficiently reduced and the reliability of the devices is poor.
The contact resistance of the gate structure and the source/drain can be efficiently reduced by forming the salicide layer on the gate structure and the source/drain. In the view of the logic circuit device, the operation rate can be increased by forming the salicide layer. But in the view of the memory device, the shallow junction of the source/drain region becomes thinner as the salicide layer is formed on the source/drain region, and thus serious leakage occurs at the capacitor electrically coupled to the source/drain region in the memory device.
SUMMARY OF THE INVENTION
The invention provides a method of manufacturing a salicide layer. By using the invention, the resistance of the gate structure can be reduced and the ability of the logic circuit device is enhanced.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method of manufacturing a salicide layer. A substrate having a memory region and a logic circuit region is provided. The memory region comprises a first gate structure and a first source/drain region and the logic circuit region comprises a second gate structure and a second source/drain region. A protective layer is formed over the memory region. A first salicide layer is formed on the second gate structure and the second source/drain region in the logic circuit region. The protective layer is removed to expose the first gate structure and the first source/drain region. A dielectric layer is formed over the substrate. A portion of the dielectric layer is removed to expose the first gate structure and the first salicide layer above the second gate structure. A second salicide layer is formed on the first and the second gate structure. Since the formation of the first and the second salicide layer is performed after the first and the second source/drain region are formed in the substrate, the resistance of the gate structure can be efficiently reduced and the reliability of the devices is high. Additionally, because of the formation of the second salicide layer, the resistance of the first and the second gate structure is reduced and the ability of the logic circuit device is enhanced.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 5539256 (1996-07-01), Mikagi
patent: 5792684 (1998-08-01), Lee et al.
patent: 5869396 (1999-02-01), Pan et al.
patent: 5891785 (1999-04-01), Chang
patent: 6001721 (1999-12-01), Huang
patent: 6004843 (1999-12-01), Huang
patent: 6015748 (2000-01-01), Kim et al.

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