Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-03-21
2001-07-10
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
43
Reexamination Certificate
active
06258665
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a non-volatile semiconductor memory device and a method for manufacturing the same and, particularly, an improvement in or relating to the manufacturing step of forming the laminated gate structure thereof.
An EEPROM is a kind of non-volatile semiconductor memory device in which data can be electrically rewritten or reloadable and, known as such a memory device is an MOS transistor which comprises a laminated gate structure consisting of a charge storage layer (floating gate) and a control gate.
FIG. 1A
is a plan view showing the memory cells of an FETMOS type EEPROM which is one type of EEPROM, and
FIG. 1B
is a sectional view taken along the line
1
B—
1
B in FIG.
1
A.
As shown
FIGS. 1A and 1B
, on a p-type silicon substrate (or a p-type well)
100
, there is formed a thermally oxidized oxide or thermal oxide film (SiO
2
) constituting element isolation regions. The element isolation regions
101
define element regions
102
in the surface of the substrate
100
. In the portion of the substrate
100
which lies under the element isolation regions
101
, p+ type channel stoppers
103
are formed. In the element regions
102
, n+ type source and drain regions
110
are formed. The portion of the respective element region
102
which lies between the source and drain regions
110
constitutes a channel region
104
. Formed on the channel region
104
is a thin oxide film (SiO
2
)
105
through which a tunnel current can be made to flow. The oxide film
105
is a gate insulation film. On the oxide film
105
, a floating gate
106
, an inter-layer insulation film
107
and a control gate
108
are successively formed. The inter-layer insulation film
107
insulates the floating gate
106
and the control gate from each other and, at the same time, capacitively couple said control gate
108
and said floating gate
105
to each other. Due to this, the inter-layer insulation film
107
is formed of, e.g. silicon dioxide or a so-called ONO (oxide-nitride-oxide) film formed by successively laminating silicon dioxide, silicon nitride and silicon dioxide one upon another. Further, the laminated gate structure consisting of the floating gate
106
, the inter-layer insulation film
107
and the control gate
108
is formed in a continuous patterning manner using a photo resist mask (not shown) patterned into a control gate pattern. Due to this, the edges of the floating gate
106
and the edges of the control gate
108
are matched with each other. The source and drain regions
110
are formed by injecting an n-type impurity into the substrate
100
by means of ion implantation, using as a mask the laminated gate structure and the element isolation regions
101
, respectively.
In the case of the memory cells shown in
FIGS. 1A and 1B
, used for the element isolation regions
101
is a thermally oxidized oxide film or thermal oxide film formed by the use of the LOCOS (Local Oxidation Of Silicon) method.
FIGS. 2A and 2B
show typical manufacturing process according to the LOCOS method.
As shown in
FIG. 2A
, according to the LOCOS method, a nitride film (Si
3
N
4
)
200
is formed in the surface portions of the substrate
100
other than the surface portions of the substrate
100
in which the element isolation regions are formed. After this, as shown in
FIG. 2B
, the surface of the substrate
100
is thermally oxidized to a considerable thickness. Since the nitride film
200
functions as a barrier film against oxidation, the thermal oxide film (SiO
2
) is formed on the (surface) portions of the surface of the substrate
100
which are not covered by the nitride film
200
. The thermal oxide film thus formed constitutes the element isolation regions
101
. Further, in
FIG. 2A
, the reference numeral
300
denotes a buffer oxide film.
In the case of the LOCOS method, as is well known, wedge-shaped oxide films known as “bird's beaks” in the respective interface between the nitride film
200
and the substrate
100
. The bird's beaks result in causing a conversion error between the designed structure and the actually completed structure. Due to this, each element isolation region
101
, that is, the actual width dimension S
A
of the element isolation region
101
becomes larger by, e.g. an amount corresponding to the conversion error than the designed width dimension S
D
. According to the LOCOS method which has such a defect, it is very difficult to form each element isolation region
101
the smallest width of which is 0.5 &mgr;m or less.
Further, in the case of employing the LOCOS method, the portion of the thermal oxide film which is formed in the interior of the substrate
100
is only about half of the whole thickness thereof. Due to this, the element isolating ability exhibited in the interior of the substrate
100
is scanty, and it is also difficult to narrow the interval for element isolation.
Further, the remaining portion of the thermal oxide film comes out to the surface of the substrate
100
, so that, in the surface of the substrate, “differences in level” are caused. The “differences in level” thus caused in the surface of the substrate
100
results in lowering the processing margin in the lithography step, so that even the formation of fine patterns are made difficult.
As an element isolation technique for overcoming such a difficulty, the trench element isolation technique has come to be developed according to which trenches are formed in the substrate, and the interiors of the trenches are filled up with an insulation material.
FIG. 3A
is a plan view of the memory cell of an FETMOS type EEPROM formed by the use of the trench element isolation technique, and
FIG. 3B
is a sectional view taken along the line
3
B—
3
B in FIG.
3
A. In
FIGS. 3A and 3B
, the portions corresponding to those shown in
FIGS. 1A and 1B
are referenced by the same reference numerals for omission of the description thereof and for giving a description of only different portions.
As shown in
FIGS. 3A and 3B
, in a substrate
100
, trenches
111
for element isolation are formed. The interiors of the trenches
111
are filled with an element isolating insulation material such as, e.g. silicon dioxide, whereby trench type element isolation regions
112
are formed.
In the trench type element isolation regions
112
, no bird's beak is produced; and thus, no conversion error exists between the designed structure and the actually completed structure.
Further, in the case of the respective trench type element isolation region
112
, the portion thereof which is formed in the interior of the substrate
100
can be determined depending on the depth of the trench
111
, so that element isolation regions formed deeply in the interior of the substrate can be realized. As a result, the element isolation ability can be enhanced; and the interval required for isolation of the elements from each other can be more reduced than in the case of the element isolation regions formed in accordance with the LOCOS method. Due to this, the interval for element isolation can be decreased to a substantial degree. In this way, by introducing the trench element isolation technique, the miniaturization of the element isolation regions becomes possible.
However, in the case of the memory cells of an EEPROM, there is another structural portion which is an obstacle to the miniaturization. That is “wings”
113
of each floating gate
106
. The “wings”
113
are formed in a state extended onto the element isolation regions. Due to the fact that the floating gates
106
have the “wings”
113
, the mutually opposed areas of each floating gate
106
and the associated control gate
108
spread, so that the capacitance between the floating gate
106
and the control gate
108
increases. However, the design-wise minimum dimension is restricted by the distance between the “wings”
113
, that is, the dimension of a “slit”
114
for separating the floating gates
106
from each other, so that the merit due to the trench element isolation tech
Aritome Seiichi
Narita Kazuhito
Shimizu Kazuhiro
Banner & Witcoff , Ltd.
Fourson George
Kabushiki Kaisha Toshiba
Pham Thanh
LandOfFree
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