Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1998-06-17
2001-01-16
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S253000, C438S250000, C438S258000, C438S685000, C438S686000, C438S393000
Reexamination Certificate
active
06174766
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. More particularly, the invention relates to a semiconductor integrated circuit having a metallic oxide dielectric capacitor and a method of manufacturing the integrated circuit.
BACKGROUND OF THE INVENTION
Previously, a metallic oxide dielectric has been used as a capacitor insulating film of a semiconductor memory device because it has high dielectric properties and/or high ferroelectric properties. For example, the metallic oxide dielectric may contain a layer of bismuth oxide SrBi
2
Ta
2
O
9
or titanium zirconate (Pb(Ti, Zr)O
3
) to exhibit the ferroelectric properties. If the metallic oxide dielectric is exposed to a reducing atmosphere, crystallized metal ions are reduced while oxide ions are released, and thus, oxide defects are formed in the dielectric. As a result, various characteristics of the metal oxide dielectric deteriorate (e.g. an increase in leak current, a degradation of remanence characteristics, etc.). Accordingly, when a capacitor having a metallic oxide dielectric is mounted on a silicon integrated circuit, the capacitor should be prevented from being exposed to a reducing atmosphere as much as possible during the manufacturing process of the integrated circuit.
Also, a noble or inert metal such as platinum (“Pt”) which resists oxidation should be used as an electrode of the capacitor having the metal oxide dielectric. Therefore, one must be careful to prevent a reaction between such metal forming the capacitor electrode and the metal wiring which is electrically connected to the capacitor electrode. If the two metals react, the properties of the capacitor deteriorate.
In order to better understand the concepts described above and to even further appreciate the achievements of the present invention, three conventional examples will be described below.
The first conventional example is disclosed in H. Kokie, et al., “A 60-ns 1-Mb Nonvolatile Ferroelectric Memory with a Nondriven Cell Plate Line Write/Read Scheme”,
IEEE Journal of Solid-State Circuits
, Vol. 31, No. 11, (Nov. 1996). The first conventional example is illustrated in
FIGS. 19
to
26
and shows a method of manufacturing a ferroelectric memory device using titanium zirconate (“PZT”) as a metal oxide dielectric. As described above, PZT has high ferroelectric properties.
As shown in
FIG. 19
, the ferroelectric memory device is roughly partitioned into a memory cell array section
34
and a peripheral CMOS circuit section
33
. In the memory cell array section
34
, ferroelectric capacitors are regularly disposed. Also, the peripheral CMOS circuit section
33
includes CMOS transistor units that each contain a p-type MOS (“PMOS”) transistor
8
and an n-type MOS (“NMOS”) transistor
7
as a unit.
As shown in
FIG. 20
, the device is manufactured by providing a silicon substrate
1
having a memory cell array section
34
and a peripheral CMOS circuit section
33
. Then, a memory cell array containing n-type MOSFETs is formed in the memory cell array section
33
, and PMOS transistors
7
and NMOS transistors
8
are formed in the peripheral CMOS circuit section
33
. Each of the MOS transistors in the device comprises a silicon doping layer or a source/drain region formed in silicide and comprises a gate electrode
5
.
After the MOS transistors are formed, a silicon oxide film (i.e. an NSG film)
9
is grown over the transistors via a chemical vapor deposition (“CVD”) process, and a boron phosphorus added silicon oxide (“BPSG”) film
10
is grown on the NSG film
9
via a CVD process. After the BPSG film
10
is grown, it is reflowed and flattened.
Then, as shown in
FIG. 21
, a Ti electrode adhesive film
11
and a Pt lower capacitor electrode film
12
are sequentially formed on the BPSG film
10
via a sputtering process, and a PZT precursor is formed on the Pt lower capacitor electrode
12
via a spin coating method. Then, the PZT precursor is crystallized into a PZT film
13
by subjecting the precursor to an annealing process at about 600° C. A photoresist
15
having a pattern corresponding to the shape of the Pt lower capacitor electrode
12
of the capacitor is then formed on the PZT film
13
.
Then, as shown in
FIG. 22
, portions of the PZT film
13
, the Pt lower capacitor electrode film
12
, and the Ti electrode adhesive film
11
are removed via an ion milling process, and the photoresist
15
is peeled off of the remaining portions of the PZT film
13
. Afterwards, a first recovery annealing process is conducted in an oxygen atmosphere for eliminating the etching damage caused by the ion milling process and the removal of the photoresist
15
.
As shown in
FIG. 23
, a Pt upper capacitor electrode film
14
is formed via a sputtering process, and a photoresist
15
that is patterned according to the shape of the upper electrode of the capacitor is formed on the film
14
. Then, portions of the film
14
are removed by conducting an ion milling process while using the photoresist
15
as a mask to form the upper electrode
14
of the capacitor. As a result, a ferroelectric capacitor
16
is formed via the Ti electrode adhesive film
11
, the Pt lower capacitor electrode
12
, the PZT film
13
(i.e. the metal oxide dielectric), and the Pt upper capacitor electrode
14
. Afterwards, a second recovery annealing process is conducted in an oxide atmosphere to remove the etching damage formed by the ion milling process and the removal of the photoresist
15
. As shown in
FIG. 24
, a capacitor cover insulating film (i.e. a silicon oxide film)
19
is formed on the ferroelectric capacitor
16
via a plasma CVD method using silane gas (SiH
4
) and oxygen gas as a raw material.
As shown in
FIG. 25
, transistor contact holes (i.e. first contact holes)
20
and capacitor contact holes (i.e. second contact holes) are formed in the semiconductor device. The first contact holes
20
extend to the gate electrodes and the source/drain regions of the MOS transistors, and the second contact holes
22
extend to the upper capacitor electrode
14
and the lower capacitor electrode
12
of the capacitors
16
. Such holes
20
and
22
are created via a patterning process while using a photoresist (not shown) as a mask. After the holes
20
are created, a laminating film
21
consisting of a Ti adhesive film and a first barrier film of TiN is formed over the entire surface via a sputtering method.
In
FIG. 26
, an Al wiring metal film
26
and a TiN reflection preventing film
25
are sequentially formed on the entire surface. Then, the first layer Al wiring
26
, the TiN reflection preventing film
25
, and the laminate film
21
are patterned via a known process using a mixed gas consisting of Cl
2
and BCl
3
.
As shown in
FIG. 19
, an interlayer insulating film
27
is formed on the patterned first layer Al wiring
26
, and through-holes
28
are formed in the film
27
that extend to the first layer Al wiring
26
. Then, tungsten
32
is embedded in the through-holes
28
by growing tungsten
32
via a CVD method and etching back the tungsten
32
. Then, a second layer Al wiring
30
is formed over the interlayer insulating layer
27
and the tungsten
32
.
The second conventional example is disclosed in
FIG. 13
of Japanese Patent Unexamined Publication No. Hei 6-275792. The second conventional example is illustrated in
FIGS. 27
to
31
and shows a method of manufacturing a ferroelectric memory device having a metal oxide dielectric.
As shown in
FIG. 27
, a BPSG film
10
is formed over MOS transistors and is flattened. Then, a Ti electrode adhesive film
11
is formed on the BPSG film
10
, and a Pt lower capacitor electrode film
12
is formed on the adhesive film
11
. Then, the portions of the adhesive film
11
and electrode film
12
are removed to form the lower capacitor electrode
12
of the capacitor.
As shown in
FIG. 28
, a PZT film
13
is grown over the surface of the semiconductor device, and a Pt upper capacitor electrode film
14
is grow
Hayashi Yoshihiro
Inoue Naoya
Kobayashi Sota
NEC Corporation
Smith Matthew
Sughrue Mion Zinn Macpeak & Seas, PLLC
Yevsikov V.
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