Semiconductor memory device allowing reduction in a number...

Details Semiconductor memory device allowing reduction in a number... Semiconductor memory device allowing reduction in a number...

2000-05-04

2001-04-10

Nelms, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

Multiplexing

C365S189050, C365S230020, C365S230080

Reexamination Certificate

active

06215704

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and particularly a semiconductor memory device allowing reduction in number of external pins which are employed for external transmission of signals.
2. Description of the Background Art
A semiconductor memory device performs input/output of data signals as well as storage thereof based on externally supplied control signals and address signals. These signals are transmitted via pins arranged on a chip.
FIG. 26
shows a pin arrangement of a conventional semiconductor memory device
500
.
A pin arrangement of a non-synchronous SRAM (Static Random Access Memory) is shown in
FIG. 26
as an example of a pin arrangement of a conventional semiconductor memory device.
Referring to
FIG. 26
, control pins
1
-
5
are employed for input of control signals such as a chip select signal, a write control input signal and an output enable signal. Address pins A
0
-A
15
are provided for input of respective bits of an address signal. In the following description, each bit of the address signal may also be referred to as an “address bit”. DQ
1
-DQ
15
indicate DQ pins for input/output of the respective bits of an I/O data signal. In the following description, each bit of the I/O data signal may also be referred to as a “data bit”.
In semiconductor memory device
500
, the I/O data signal of 16 bits are externally read or written in response to the address signal of 16 bits.
Semiconductor memory device
500
further includes pins for receiving a ground potential VSS and a power supply voltage VCC, respectively. A pin indicated by “NC” is an unconnected pin.
In the conventional semiconductor memory device, as described above, the independent pins are provided for the signals of different functions, respectively.
However, capacities and functions of the memory devices have been improved. This results in increase in number of the bits of the address signal for selecting the memory cell and the bits of the I/O data signal which are simultaneously input/output, and also results in disadvantages such as increase of the control signals due to addition of control functions. Thereby, the device employs more pins, which increases a chip size of the device. Conversely, semiconductor memory devices such as an asynchronous SRAM have been employed in many devices such as portable telephones. For such employment, it is important to reduce a layout area.
With increase in pin number, the pins which operate simultaneously with each other increase in number, and therefore such a problem arises in the input buffer circuit, which receives data supplied through the pins, that the sum of consumed currents increases due to through-currents of transistors forming an input first stage.
SUMMARY OF THE INVENTION
An object of the invention is to provide a semiconductor memory device, which is provided with pins having integrated functions of address pins and data I/O pins, and thereby can reduce a total number of pins so that increase in chip size can be suppressed even in a structure having an increased capacity and improved functions.
In summary, a semiconductor memory device for performing input/output of a data signal of M bits (M: natural number) in response to an address signal of N bits (N: natural number) includes a memory cell array, an address decode circuit, a data I/O circuit, a plurality of multi-function terminals, a first control terminal, a second control terminal, a plurality of address register circuits and a plurality of data register circuits.
The memory cell array has a plurality of memory cells arranged in rows and columns. The address decode circuit selects the memory cells of M in number from the plurality of memory cells in response to a combination of the respective bits of the address signal. The data I/O circuit performs data input/output with respect to the selected m memory cells. The plurality of multi-function terminals are commonly used by the input of the address signal and the input/output of the data signal. The first control terminal receives a first control signal for instructing input of the address signal to the plurality of multi-function terminals. The second control terminal receives a second control signal for instructing input/output of the data signal to the plurality of multi-function terminals. The plurality of address register circuits are provided between the plurality of multi-function terminals and the address decode circuit, respectively, and each respond to activation of the first control signal by taking in the level of the signal supplied to the corresponding one of the plurality of multi-function terminal, and transmitting the level to the address decode circuit. The plurality of data register circuits are provided between the plurality of multi-function terminals and the data I/O circuit, respectively, and each respond to the activation of the second control signal by transmitting the data signal between the corresponding one of the plurality of multi-function terminals and the data I/O circuit.
Accordingly, a major advantage of the invention is that the pins can be reduced in total number because the structure is provided with the multi-function terminals or pins which can execute both the input of the address signal and the input/output of the I/O data signal. Consequently, the chip size of the semiconductor memory device can be reduced.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.


REFERENCES:
patent: 4939692 (1990-07-01), Kendall
patent: 5249160 (1993-09-01), Wu et al.
patent: 5587957 (1996-12-01), Kowalczyk et al.
patent: 5719878 (1998-02-01), Yu et al.
patent: 6104664 (2000-08-01), Ohno
patent: 4-328384 (1992-11-01), None
patent: 6-76581 (1994-03-01), None

Affiliated with

Also associated with

Rating

Semiconductor memory device allowing reduction in a number... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory device allowing reduction in a number..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device allowing reduction in a number... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2542412