Method of fabricating field effect transistor

Details Method of fabricating field effect transistor Method of fabricating field effect transistor

1999-04-28

2001-05-08

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S305000, C438S586000

Reexamination Certificate

active

06228730

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method of fabricating a field effect transistor. More particularly, the present invention relates to a method of fabricating a field effect transistor with a shallow junction.
2. Description of Related Art
The field effect transistor is one of the most important electrical devices in the integrated circuit. As the size of the semiconductor device is reduced, many improvements have also been made in the steps for fabricating the transistor.
Conventionally, the process of fabricating a transistor is to form, after a gate is formed on a substrate, a lightly doped drain (LDD) in a substrate of a gate. Spacers are formed adjacent to both sides of the gate, while an ion implantation step is preformed with the spacers serving as the mask to form a source/drain (S/D) region in the substrate. A plug is formed for conduction so that the gate, source, and drain of the transistor are connected to the circuits. As the material of the plug is typically a metal conductor, and conduction between the source/drain region and the plug is not as perfect as expected. To improve the conduction between the plug and the S/D region, a metal silicide is usually formed on the surface of the S/D region.
The metal silicide is typically formed by a self-aligned silicide (salicide) process. A metal layer is formed to cover the gate and the S/D region after the S/D region is formed. A high temperature thermal process is then performed to produce a reaction between the metal layer and the silicon in the S/D region. As a result, a metal silicide is formed to reduce sheet resistance in the S/D region.
However, there are some problems associated with this method for forming the metal silicide. For example, the metal layer reacts with the silicon in the S/D region during metal silicide formation. A part of the structure in the S/D region is then damaged, causing problems of a direct contact between the metal silicide and the substrate and thus a failure of the device.
SUMMARY OF THE INVENTION
The present invention provides a method of fabricating a field effect transistor. A thicker metal silicide is formed as a contact in the S/D region to reduce a sheet resistance of the S/D region, while ensuring the integrity of the S/D region so as to improve the performance of the field effect transistor.
The invention provides a method of fabricating a field effect transistor. A substrate with a gate is provided in the invention, wherein the gate includes a dielectric layer and an electrode. A liner oxide and a first spacer are formed adjacent to sidewalls of the gate. An epitaxial silicon layer is then formed on the first spacer on the substrate. With the gate and the first spacer serving as the mask, an ion implantation step is performed to form a shallow S/D extension junction in the substrate below the epitaxial silicon layer. An oxide layer and a second spacer are formed adjacent to the first spacer. With the gate, the first spacer, and the second spacer serving as the mask, a further ion implantation step is performed to form the S/D region in the substrate. A self-aligned silicide process is performed to transform the epitaxial silicon layer at both sides of the second spacer into the metal silicide, thus completing the process of the field effect transistor.
The invention includes a feature to form an epitaxial silicon layer at both sides of the first spacer on the substrate before forming the shallow S/D extension junction. This epitaxial silicon layer provides enough silicon atoms consumed for forming the metal silicide in the subsequent step. As a result, the shallow S/D extension junction and the S/D region are not damaged by the nitridation reaction and a thinner shallow S/D extension junction is formed. Furthermore, since the shallow S/D extension junction is not formed when the epitaxial silicon layer is formed, the high temperature during the epitaxial silicon layer formation does not cause a diffusion of the doped ions in the shallow S/D extension junction.
In addition, this epitaxial silicide layer also allows the formation of a thicker metal silicide on the S/D region. The thicker metal silicide can reduce the sheet resistance of the S/D region, so as to improve the effectiveness of the field effect transistor and its operating speed.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 5153145 (1992-10-01), Lee et al.
patent: 5196360 (1993-03-01), Doan et al.
patent: 5200352 (1993-04-01), Pfiester
patent: 5241193 (1993-08-01), Pfiester et al.
patent: 5319232 (1994-06-01), Pfiester
patent: 5679589 (1997-10-01), Lee et al.

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