Electrical computers and digital processing systems: memory – Addressing combined with specific memory configuration or... – Addressing cache memories
Reexamination Certificate
1998-02-10
2001-07-17
Thai, Tuan V. (Department: 2186)
Electrical computers and digital processing systems: memory
Addressing combined with specific memory configuration or...
Addressing cache memories
C711S101000, C711S102000, C711S103000
Reexamination Certificate
active
06263398
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates, in general, to the field of non-volatile integrated circuit (“IC”) memory devices. More particularly, the present invention relates to an integrated circuit memory device incorporating a non-volatile memory array and a relatively faster access time memory cache integrated monolithically therewith.
As the performance of computer central processing units (“CPUs”) has increased dramatically in recent years, this performance improvement has far exceeded that of any corresponding increase in the performance of computer main memory. Typically, main memory has been made up of numbers of asynchronous dynamic random access memory (“DRAM”) integrated circuits and it was not until the introduction of faster static random access memory (“SRAM”) cache memory that the performance of systems with DRAM main memory improved. This performance improvement was achieved by making a high speed locally-accessed copy of memory available to the CPU so that even during memory accesses, the CPU would not always need to operate at the slower speeds of the system bus and the main memory DRAM. This method of copying memory is referred to as “caching” a memory system and is a technique made possible by virtue of the fact that much of the CPU accesses to memory is directed at localized memory address regions. Once such a region is copied from main memory to the cache, the CPU can access the cache through many bus cycles before needing to refresh the cache with a new memory address region. This method of memory copying is advantageous in memory Read cycles which, in contrast to Write cycles, have been shown to constitute 90% of the external accesses of the CPU.
As mentioned previously, the most popular hardware realization of a cache memory employs a separate high-speed SRAM cache component and a slower but less expensive DRAM component. A proprietary Enhanced DRAM (EDRAM®) integrated circuit memory device, developed by Enhanced Memory Systems, Inc., integrates both of these memory elements on one chip along with on-chip tag maintenance circuitry to further enhance performance of computer main memory over separate SRAM and DRAM components. Access to the chip is provided by a single bus. Details of the EDRAM device are disclosed and claimed in the aforementioned United States patents.
DRAM memory devices are designed utilizing a volatile, dynamic memory cell architecture, typically with each cell comprising a single transistor and capacitor. They are “volatile” in the sense that upon powerdown, the memory contents are lost and “dynamic” in the sense that they must be constantly refreshed to maintain the charge in the cell capacitor. The refresh operation is accomplished when the memory contents of a row of cells in the memory array is read by the sense amplifiers and the logic states in the cells that have been read are amplified and written back to the cells. As mentioned previously, DRAM is used primarily for memory reads and writes and is relatively inexpensive to produce in terms of die area. It does, however, provide relatively slow access times.
On the other hand, SRAM devices are designed utilizing a volatile static memory cell architecture. They are considered to be “static” in that the contents of the memory cells need not be refreshed and the memory contents may be maintained indefinitely as long as power is supplied to the device. The individual memory cells of an SRAM generally comprise a simple, bi-stable transistor-based latch, using four or six transistors, that is either set or reset depending on the state of the data that was written to it. SRAM provides much faster read and write access time than DRAM and, as previously mentioned, is generally used as a memory cache. However, because the individual memory cell size is significantly larger, it is much more expensive to produce in terms of on-chip die area than DRAM and it also generates more heat. Typical devices cost three to four times that of DRAM.
In contrast to DRAM and SRAM, various types of non-volatile memory devices are also currently available, by means of which data, can be retained without continuously applied power. These include, for example, erasable programmable read only memory (“EPROM”) devices, including electrically erasable (“EEPROM”) devices, and Flash memory. While providing non-volatile data storage, their relatively slow access times (and in particular their very slow “write” times) present a significant disadvantage to their use in certain applications.
In contrast, ferroelectric memory devices, such as the FRAM® family of solid state, random access memory integrated circuits available from Ramtron International Corporation provide non-volatile data storage through the use of a ferroelectric dielectric material which may be polarized in one direction or another in order to store a binary value. The ferroelectric effect allows for the retention of a stable polarization in the absence of an applied electric field due to the alignment of internal dipoles within the Perovskite crystals in the dielectric material. This alignment may be selectively achieved by application of an electric field which exceeds the coercive field of the material. Conversely, reversal of the applied field reverses the internal dipoles.
Data stored in a ferroelectric memory cell is “read” by applying an electric field to the cell capacitor. If the field is applied in a direction to switch the internal dipoles, more charge will be moved than if the dipoles are not reversed. As a result, sense amplifiers can measure the charge applied to the cell bit lines and produce either a logic “1” or “0” at the IC output pins. In a conventional two transistor/two capacitor (“2C/2T”) ferroelectric memory cell, (one transistor/one capacitor “1T/1C” devices have also been described) a pair of data storage elements are utilized, each polarized in opposite directions. To “read” the state of a 2T/2C memory cell, both elements are polarized in the same direction and the sense amps measure the difference between the amount of charge transferred from the cells to a pair of complementary bit lines. In either case, since a “read” to a ferroelectric memory is a destructive operation, the correct data is then restored to the cell during a precharge operation.
In a simple “write” operation, an electric field is applied to the cell capacitor to polarize it to the desired state. Briefly, the conventional write mechanism for a 2T/2C memory cell includes inverting the dipoles on one cell capacitor and holding the electrode, or plate, to a positive potential greater than the coercive voltage for a nominal 100 nanosecond (“nsec.”) time period. The electrode is then brought back to circuit ground for the other cell capacitor to be written for an additional nominal 100 nsec.
In light of the foregoing, it would be highly advantageous to provide a non-volatile memory device that provides the traditional benefits of non-volatile memory retention in the absence of applied power yet also provides the enhanced access times approaching that of other memory technologies when utilized as an on-chip integrated cache in conjunction with a non-volatile memory array.
SUMMARY OF THE INVENTION
Disclosed herein is an integrated circuit memory device incorporating a non-volatile memory array and a relatively faster access time memory cache integrated monolithically therewith which improves the overall access time in page and provides faster cycle time for read operations. In a particular embodiment, the cache may be provided as SRAM and the non-volatile memory array provided as ferroelectric random access memory (for example, FRAM®) wherein on a read, the row is cached and the write back cycle is started allowing subsequent in page reads to occur very quickly. If in page accesses are sufficient the memory array precharge in a ferroelectric based memory array may be hidden and writes can occur utilizing write back or write through caching. In alternative embodiments, the non-volatile memory array may comprise EPROM, EEPROM or Flash memory i
Alwais Mike
Carrigan Donald G.
Taylor Craig
Anderson Matthew D.
Hogan & Hartson LLP
Kubida, Esq. William J.
Ramtron International Corporation
Thai Tuan V.
LandOfFree
Integrated circuit memory device incorporating a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Integrated circuit memory device incorporating a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated circuit memory device incorporating a... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2529939