Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-02-12
2001-05-15
Smith, Matthew (Department: 2825)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S067000, C257S383000
Reexamination Certificate
active
06232637
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to integrated circuit fabrication and, more particularly, to forming active transistor devices in dissimilar elevation planes and interconnecting those devices with minimum lateral space requirement.
2. Description of the Related Art
Active devices are well known For example, active devices are classified as any device which is not passive. A transistor is but one example of an active device. Transistors are therefore regarded as a basic building block of an integrated circuit. Transistor fabrication typically involves forming source/drain impurity regions (hereinafter “junctions”) within a single crystalline silicon substrate and gate conductors spaced from the substrate by a gate dielectric aged between the junctions. Ion implantation of dopants is primarily used to form junctions. Alternatively, although less often used, the junctions may be formed by diffusion doping. Ion implantation involves placing energetic, charged atoms or molecules directly into the substrate surface. The number of implanted dopant atoms entering the substrate is more easily controlled using ion implantation. Ion implantation results in junctions having a majority carrier opposite that of the surrounding bulk substrate or well area.
Because of the increased desire to build faster and more complex integrated circuits, it has become necessary to form relatively small, closely spaced multiple transistors within a single integrated circuit. Whenever the integrated circuit involves parallel coupling of numerous transistors, a source junction of one transistor may be mutually coupled to a source junction of another transistor. Further, it may be necessary to couple a drain junction of one transistor to a drain junction of another transistor. Mutual source or drain junctions are commonly used to provide such coupling. Mutual source or drain junctions are typically formed within one elevation level (i.e., substrate of an integrated circuit). Thus, transistors pairs can involve a layout which allows the transistors to share a mutual junction.
FIG. 1
illustrates the utility of mutual source or drain junctions.
The circuit diagram of
FIG. 1
depicts a portion of a two input NAND gate
10
. The output from NAND gate
10
is shown fed into the input of inverter
20
. Similar to NAND gate
10
, only a portion of inverter
20
is shown. NAND gate
10
includes a pair of transistors
12
and
14
arranged in parallel. Transistors
12
and
14
share a mutual source junction
16
which provides power coupling to the transistors. Transistors
12
and
14
share a mutual drain junction
18
.
FIG. 1
illustrates the benefits of using mutual source or drain junctions in modem day integrated circuit layout. In most core logic areas of an integrated circuit there are logic gates and interconnection between those gates. A substantial portion of the core logic areas involves routing interconnect between gates or enlarging junctions to accommodate mutual connection to those junctions. In either instance, the conventional solution to high density core layout is the occupation of lateral area.
Unfortunately, since transistors are generally formed within the silicon-based substrate of an integrated circuit, the number of transistors per integrated circuit is limited by the available lateral area of the substrate. Moreover, transistors cannot employ the same portion of a substrate, and increasing the area occupied by the substrate is an impractical solution to this problem. Thus, packing density of an integrated circuit is somewhat sacrificed by the common practice of forming transistors exclusively within a substrate having a limited amount of area. It is therefore desirable that a semiconductor fabrication process be developed for the formation of more densely packed transistors. Such a process would lead to an increase in circuit speed as well as an increase in circuit complexity.
SUMMARY OF THE INVENTION
The problems outlined above are in large part solved by the fabrication process of the present invention. That is, a method for forming doped polysilicon structures elevated above an integrated circuit substrate is provided. The elevated, doped polysilicon structures provide another elevation plane on which and into which active devices can be drawn. This ensures a multi-level transistor fabrication method. Of prime importance, however, is the interconnection between transistors on one level (i.e., within the single crystalline substrate or “substrate”) and transistors on another level (i.e., in the polycrystalline substrate or “elevated polysilicon substrate”). In instances where a common source (or drain) connection is needed, improvements to the interconnect scheme is provided.
In a multi-level integrated circuit, the elevated transistor and, more specifically, the elevated source/drain junctions are located a spaced distance above the substrate and the substrate-embodied transistors. Active areas are formed in the elevated polysilicon substrate. Therefore, junctions of transistors located within the substrate must be efficiently coupled to the source/drain junctions (i.e., elevated junctions) within the elevated polysilicon substrate. Furthermore, gate conductors disposed upon the substrate may also be coupled to the elevated junctions. An integrated circuit having such a configuration encourages the formation of transistors within a substrate and at an elevation removed from the substrate, providing for a more densely packed integrated circuit.
According to one embodiment, a transistor is provided which is disposed upon and within the substrate. The transistor includes a gate conductor spaced between a pair of junctions. A primary interlevel dielectric may be deposited across the transistor and the substrate. A select portion of an upper surface of the primary interlevel dielectric is then removed to form a trench extending horizontally above and laterally removed from the substrate. Polycrystalline silicon, i.e., polysilicon may be chemical vapor deposited (“CVD”) across the primary interlevel dielectric and into the trench. Portions of the polysilicon exclusive of the trench may then be removed to form a polysilicon structure bounded exclusively within the trench.
The polysilicon structure is implanted with a particular type of dopant such that the structure may have an opposite type of majority carrier as the junctions below. A secondary interlevel dielectric may then be deposited across the doped polysilicon structure and the primary interlevel dielectric. Portions of the primary and secondary interlevel dielectrics are then removed to partially expose at least one of the transistor junctions and the polysilicon structure. In fact, a portion of the upper surface of the polysilicon structure as well as the sidewall surface nearest this portion are preferably exposed. Thus, an upper portion of the exposed region of the polysilicon structure may be implanted to have the same type of majority carrier as the junctions below (i.e., the junction that had been partially exposed). A conductive material may be formed within the removed portions of the primary and secondary interlevel dielectrics to form a contiguous interconnect between the polysilicon structure and the transistor junction nearest to the structure.
In an alternate embodiment, a conductive material may be formed through the primary and secondary interlevel dielectrics to the upper surface of the gate conductor of the transistor. Further, a second polysilicon structure may be formed within the primary interlevel dielectric laterally spaced from the first polysilicon structure. It is desired that the second polysilicon structure also reside a spaced distance above and laterally from the transistor. The second polysilicon structure is preferably laterally spaced from the first polysilicon structure. The second polysilicon structure may be coupled to the nearest transistor junction by an interconnect. Additional transistors may be formed within both polysilicon structures and within
Gardner Mark I.
Kadosh Daniel
Advanced Micro Devices , Inc.
Anya Igwe U.
Conley & Rose & Tayon P.C.
Daffer Kevin L.
Smith Matthew
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