Method of self-aligned contact hole etching by...

Details Method of self-aligned contact hole etching by... Method of self-aligned contact hole etching by...

1998-06-03

2001-05-29

Wilczewski, Mary (Department: 2822)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S238000, C438S256000, C438S397000, C438S399000, C438S697000, C438S723000, C438S724000

Reexamination Certificate

active

06239011

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to processes for the manufacture of semiconductor devices and more particularly to the etching of contact openings in the manufacture of sub-micron MOSFETs.
(2) Background of the Invention and Description of Prior Art
The fabrication of integrated circuit chips comprises the formation of semiconductor devices within the surface of a single crystalline silicon wafer. The semiconductive elements of metal-oxide-silicon-field-effect-transistors (MOSFETs) are contained within the surface of the single crystalline substrate wafer and are formed by ion-implantation using the control electrode, a polysilicon gate formed over the substrate, as an implantation mask. The source and drain regions of the MOSFET are thereby self-aligned to the gate electrode.
Many variations of the principle of self alignment to the polysilicon gate have been developed to improve device performance and stability, in particular, the use of side walls along the edges of the polysilicon gate have permitted the tailoring of source and drain diffusions at the ends of the channel region to control short channel effects. These advances in MOSFET processing have resulted in high performance sub-micron sized devices of many types. The lightly-doped-drain (LDD) structure, used universally in sub-micron MOSFET technology, is a notable example of this side-wall tailoring.
The use of insulative sidewalls and caps over polysilicon conductors has also permitted the formation of self-aligned contacts (SAC) to MOSFET active elements. Self-alignment processing utilizes reactive-ion-etching (RIE) to anisotropically etch vertical walled openings, typically through insulative layers, such as silicon oxide and various silicate glasses.
Self-aligned-contacts can be made in various configurations. Typically an insulative sidewall is provided along the edge of the polysilicon gate electrode. The sidewall provides an insulative spacing between the contact and the polysilicon gate. Referring to
FIG. 1
there is shown a cross section of a silicon wafer with two adjacent MOSFETs. The configuration shown here is typical of a well known design (DASH Cell) for a dynamic random access memory(DRAM) cell. The polysilicon gate electrodes
18
form the wordlines of the DRAM. The source/drain diffusions
12
,
14
are formed by the widely used LDD process utilizing the sidewalls
27
. In subsequent processing steps, storage capacitors are formed over the semiconductive elements
14
while a bitline contact is made to the semiconductive element
12
.
The polysilicon wordlines in this example have a tungsten silicide layer
20
and a thin silicon oxide layer
22
over them. The sidewalls
27
and a top protective layer
24
are formed of silicon nitride. These layers are formed and patterned by conventional modern processing techniques well known to those in the art. An insulative layer
26
of silicon oxide is deposited over the wafer
10
followed by a silicate glass layer
28
, for example, phosphosilicate glass PSG or borophosphosilicate glass(BPSG). This layer
28
is planarized by any of several well known techniques, for example chemical mechanical polishing (CMP). An opening for the bitline contact is then defined using well known photolithographic processing methods, whereby a pattern is formed in a photoresist layer
30
. The photomask opening
32
can be made larger than the contact area at the silicon surface. The self-alignment feature also permits slight mis-alignment of the photomask because the contact at the silicon is determined by the nitride sidewall
27
.
The wafer
10
is next subjected to an RIE processing step whereby the opening
32
for the bitline contact is etched through the insulative layers
26
,
28
. The etchant gas and the RIE parameters are selected to provide vertical walls in the opening in the silicon oxide layer and a high silicon oxide etch rate selectivity, that is to say, a high silicon oxide/silicon nitride etch rate ratio. The opening
32
illustrated in
FIG. 2
was formed with an etch rate sensitivity sufficiently high that the nitride sidewalls
27
and the exposed upper portions of the nitride top cap
24
were imperceptibly etched. The layer
36
is a polymer which is formed during the etching process. Under conditions of inadequate etch rate selectivities the nitride sidewalls
27
and top nitride cap
24
etch at rates whereby the insulative spacing provided by these elements is reduced by erosion of the nitride, resulting in subsequent shorts between bitline and wordline. This is illustrated in
FIG. 3
Where the upper corners
34
of the wordlines have been exposed.
Until recently, etch rate selectivities greater than about 8:1 were not attainable without sacrificing other important aspects such as etching anisotropy. In the current technology, where dimensional features are of the order of quarter micron, it becomes increasingly more difficult to achieve a sufficiently high etch rate selectivity for this contact opening etch without aggravating deleterious side effects, for example incomplete oxide removal at the base of the contact resulting in unacceptable contact resistance.
Marks, et.al., U.S. Pat. No. 5,423,945 discloses reducing the fluorine content of the passivation polymer, and reducing the amount of free fluorine in the plasma, reduces the dissociation of the polymer. By adding a fluorine scavenger such as silicon or carbon ions to the plasma, the resultant polymer becomes carbon rich and is more resistant to dissociation. In an example, an etch rate selectivity of oxide to nitride of 15:1 was achieved by the use of a fluorine scavenger.
Yanagida, et.al., U.S. Pat. No. 5,338,399 obtain high etch rate selectivities of insulators with respect to silicon base material, while also achieving low pollution, and low silicon damage, by using cyclic fluorocarbons, for example octafluorocyclobutane (C
4
F
8
) to etch contact openings. The cyclic fluorocarbons provide a higher C/F ratio than comparable straight chain fluorocarbons which is considered beneficial for effectively depositing carbonaceous polymers.
It is widely believed that polymer formation in an RIE plasma containing fluorocarbon etchants, is largely responsible, not only for the etching anisotropy, but also for the etch rate selectivity. In the case of silicon oxide etching, the polymer formed at the etching front is rapidly dissociated by the released oxygen. However, over regions of silicon nitride, the oxygen concentration is less and the polymer is not readily dissociated, thereby providing passivation of the silicon nitride.
In order to achieve the high etch rate sensitivity to achieve the profile shown in
FIG. 2
, it was necessary to utilize etchant gases and RIE parameters which provided a relatively high steady state polymer thickness over the Si
3
N
4
. The residual polymer
36
is shown prior to its removal at the termination of the etching operation. An insufficient steady state polymer thickness leads to the profile shown in FIG.
3
. where the Si
3
N
4
has been eroded.
As device densities are increased and their geometries become smaller, new problems arise in the etching of openings for self-aligned contacts. In particular, as the dimensions of the contact openings enter the sub-quarter micron range, difficulties are encountered with clearing of insulative material from the base of the opening when etching at high SiO
2
/Si
3
N
4
selectivities. Heavy polymer formation over the silicon nitride spacers interferes with the proper clearance of insulative material at the base of the opening by bridging across the narrow opening, thereby terminating the etching. Residual oxide in the opening causes opens or unacceptably high contact resistance.
FIG. 4A
illustrates a cross section of a bitline contact opening
40
defined by a photoresist masking layer
30
. The layout is similar to that shown in
FIG. 1
except that now the spacing between the polysilicon wordlines is reduced. The width d, of the photoresist opening
40
which defines the

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