Method of fabricating a semiconductor device with silicided...

Details Method of fabricating a semiconductor device with silicided... Method of fabricating a semiconductor device with silicided...

1998-09-01

2001-06-05

Chaudhari, Chandra (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S592000, C438S655000

Reexamination Certificate

active

06242311

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device having an improved structure.
2. Background of the Related Art
As semiconductor devices become more highly integrated, the size of a MOS transistor becomes smaller, and the junction depth of its source/drain region becomes more shallow. As the junction depth of the source/drain region becomes more shallow, the sheet resistance increases because the sheet resistance of a junction is inversely proportional to the junction depth. This, in turn, raises parasitic resistance of the device.
To reduce the sheet resistance of a junction, a silicide layer may be formed on the shallow source/drain region. The silicide layer is roughly divided into a polycide formed by reaction of a refractory metal and polysilicon, and self-aligned silicide (SALICIDE) formed by reaction of a refractory metal and silicon. Titanium silicide (TiSi
2
) is widely used as the silicide.
When the silicide layer is formed on the source/drain region, a portion of the source/drain region formed of silicon is consumed to a specific depth corresponding to the thickness of the silicide layer during the suicide forming process. Accordingly, a silicide formation technique which produces a thin silicide layer with stable characteristics is helpful in fabricating VLSI devices. Furthermore, when the silicide layer is formed on a shallow junction of a source/drain region, the boundary between the silicide and silicon should be even.
A background art method of fabricating a semiconductor device having a silicide layer is explained below with reference to the attached drawings.
FIGS. 1A
to
1
H are cross-sectional views showing a semiconductor after steps of a background method of fabricating a conventional semiconductor device have been performed.
Referring to
FIG. 1A
, a semiconductor substrate
1
having a cell region and a peripheral region is first prepared. A predetermined region between the cell region and peripheral region is etched through photolithography to a predetermined depth, to form a trench which is used as an isolation region. A first insulating layer
2
is formed on the overall surface of the substrate, including the trench, and is then etched back so that the first insulating layer
2
is only in the trench.
Referring to
FIG. 1B
, a second insulating layer
3
, a first polysilicon layer
4
, a third insulating layer
5
, a metal layer
6
and a fourth insulating layer
7
are sequentially formed on the overall surface of the substrate
1
, including the first insulating layer
2
. Here, second insulating layer
3
, which is used as a gate insulating layer, is formed of an oxide layer, the third insulating layer
5
is formed of TiN, and the fourth insulating layer
7
is a cap oxide layer.
Referring to
FIG. 1C
, a first photoresist is deposited on the fourth insulating layer
7
, and patterned through exposure and development, to form a first photoresist pattern PR
1
defining gate electrode regions. The fourth insulating layer
7
, metal layer
6
, third insulating layer
5
and polysilicon layer
4
are selectively removed, using the first photoresist pattern PR
1
as a mask, to form a plurality of gate electrodes
8
a
and
8
b.
Referring to
FIG. 1D
, the first photoresist pattern PR
1
is removed, and impurity ions are implanted in a low concentration into the substrate, using gate electrodes
8
a
and
8
b
as a mask, to form LDD regions
9
. A fifth insulating layer is formed on the overall surface of the substrate, including gate electrodes
8
a
and
8
b,
and is then etched back to form fifth insulating layer spacers
10
a
and
10
b
on the sides of gate electrodes
8
a
and
8
b.
Second insulating layer
3
is then selectively etched using the fifth insulating layer spacers
10
a
and
10
b
as a mask. Here, fifth insulating layer spacers
10
a
and
10
b
are formed of a nitride layer for self-aligned contact in the following process.
Referring to
FIG. 1E
, a second photoresist is deposited on the overall surface of the substrate
1
, including the fifth insulating layer spacers
10
a
and
10
b,
and is patterned through exposure and development to form a second photoresist pattern PR
2
only on the cell region. Impurity ions are implanted in a high concentration into the exposed portions of the substrate, using the second photoresist pattern PR
2
, gate electrode
8
b
and fifth insulating layer spacer
10
b
as a mask, to form a source/drain region
11
in the peripheral region.
Referring to
FIG. 1F
, the second photoresist pattern PR
2
is then removed, and a sixth insulating layer
12
for planarization is formed on the overall surface of the substrate. Thereafter, a third photoresist is deposited on the sixth insulating layer
12
, and patterned through exposure and development to form a third photoresist pattern PR
3
only on the cell region. A portion of the sixth insulating layer
12
overlying the peripheral region is then selectively removed using the third photoresist pattern PR
3
as a mask.
Referring to
FIG. 1G
, the third photoresist pattern PR
3
is then removed, a second metal layer is formed on the overall surface of the substrate, and a silicide layer
13
is formed on the source/drain region
11
in the peripheral region, using heat treatment. Then, the remaining portions of the second metal layer are removed through a cleaning process, and a seventh insulating layer
14
is formed on the overall surface of the substrate to planarize the substrate. Portions of the sixth and seventh insulating layers
12
and
14
are then selectively removed to expose portions of the silicide layer
13
of the peripheral region and portions of the LDD region
9
of the cell region, thereby forming a plurality of contact holes
15
. Referring to
FIG. 1H
, a third metal layer is formed on seventh insulating layer
14
, including the contact holes
15
, and is selectively removed, to form a plurality of bit lines
16
.
The method of fabricating the background art semiconductor device has several problems. Source/drain leakage current increases when the silicide layer is formed on the source/drain region of the transistor. Furthermore, because it is desirable for the gate region of the transistor to have a low sheet resistance, a metal layer (or polycide layer) must be formed on the gate electrode, and a silicide formation process must be carried out while a protection layer is formed on the cell region. This complicates the gate structure and the overall device formation process. Moreover, variations in channel doping may occur due to heat cycling during the silicide formation process.
SUMMARY OF THE INVENTION
The present invention is directed to methods of fabricating a semiconductor device that substantially obviate one or more of the problems, limitations and disadvantages of the background art.
An object of the present invention is to provide a shallower junction and lower sheet resistance.
Another object of the present invention is to provide a method of fabricating a semiconductor device which prevents a silicide layer from being formed on a cell region of a transistor, while simultaneously allowing formation of a silicide layer on the gate of the transistor to reduce the sheet resistance of the gate.
The present invention can be achieved in a whole or in part by a method that includes the steps of: providing a substrate having a cell region and a peripheral region; forming at least one gate electrode on the cell region of the semiconductor substrate; and forming silicide layers on a top surface of the gate electrode and a portion of the peripheral region. Alternate methods embodying the invention may also include the steps of: forming lightly doped (LDD) regions in the semiconductor substrate using gate electrodes as a mask; forming spacers on the sides of each of the gate electrodes; forming a first insulating layer on the cell region of the semiconductor such that surfaces of the gate electrodes are exposed; altering a conductivity of a sou

Affiliated with

Also associated with

Rating

Method of fabricating a semiconductor device with silicided... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of fabricating a semiconductor device with silicided..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of fabricating a semiconductor device with silicided... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2528551