High performance self-aligned silicide process for...

Details High performance self-aligned silicide process for... High performance self-aligned silicide process for...

1994-08-30

2001-03-13

Quach, T. N. (Department: 2814)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S586000, C438S655000, C438S683000

Reexamination Certificate

active

06200871

ABSTRACT:

FIELD OF THE INVENTION
The instant invention relates to microelectronic technology and semiconductor processing, and, more specifically, to a method of fabricating a semiconductor device with self-aligned silicide regions for integrated circuits.
BACKGROUND OF THE INVENTION
Some high performance semiconductor technologies (such as complementary metal-oxide-semiconductor, CMOS, technologies used for high performance microprocessors and SRAM devices) employ self-aligned silicide regions (“salicide”) to reduce source/drain junction and gate parasitic resistance elements. As semiconductor technologies scale to the sub-half-micron minimum feature size regime, junction leakage requirements place a serious constraint on the maximum initial refractory metal (for example, titanium or cobalt) thickness. This is due to the requirement that the amount of silicon consumption over the source/drain junction regions must be reduced in order to prevent junction leakage problems. This will, however, increase the silicide sheet resistance and reduce the benefit of the salicide formation due to increased parasitic source/drain and gate resistance elements.
Several approaches have been proposed in order to overcome the above-mentioned limitations and produce low sheet resistance salicide for sub-half-micron insulated-gate field-effect transitor (IGFET) devices. One method is based on the use of elevated source/drain junction structures to allow thicker silicide but electrically shallow junctions. This method is, however, undesirable due to its need for selective silicon growth which results in added process complexity (due to the deposition selectivity requirement) and cost. Thus, there has been a preference to avoid elevated source/drain junction structures in IC manufacturing.
Recently, another method has been proposed to lower the source/drain junction and gate sheet resistance values. This method is based on the combination of self-aligned silicide and selective chemical-vapor deposited tungsten (“CVD-W”) processes. This method employs a relatively thin layer of initial refractory metal layer (for example the titanium layer would be less than 500 Å thick) to form a salicide structure without excessive silicon consumption. The salicide process is then followed by selective chemical-vapor deposition of tungsten (“CVD-W”) to further reduce the source/drain junction and gate sheet resistance values due to the CVD-W/TiSi
2
stack structure over these regions. This method, however, has some drawbacks. First, it requires a selective CVD-W process which makes it a rather complex and expensive process (due to the strict deposition process selectivity requirement). Second, the CVD-W to TiSi
2
contact resistance can become rather high due to the action of fluorine during the CVD-W process, which can result in the formation of a nonvolatile insulating TiF
x
compound at the CVD-W/TiSi
2
interface. Selective CVD-W processes usually employ a process medium consisting of WF
6
, SiH
4
, and H
2
. Tungsten is selectively deposited (typically at a substrate termperature of 300° C.) on the regions with exposed silicon and/or metallic coating. The TiF
x
formation process may occur due to presence of fluorine caused by WF
6
. Third, this method may introduce the formation of wormholes in silicon due to CVD-W, which can result in excessive junction leakage. Thus, it is desirable to employ a process which can produce low sheet resistance salicide without a need for selective CVD-W.
SUMMARY OF THE INVENTION
This invention provides a fully self-aligned processing technique for fabrication of sub-half-micron salicided devices (including IGFETs) with very small, on the order of less than 300 Å, silicon consumption and very low source/drain junction and gate sheet resistance values. An embodiment of the present invention is a method which does not require any selective deposition processes and employs standard silicon processing resources. The method of the present invention also provides a silicide local interconnect as a byproduct of the fabrication process flow.
One embodiment of the instant invention is a method for fabricating a semiconductor device with a self-aligned silicide region, the method comprising: providing a semiconductor substrate of a first conductivity type, the semiconductor substrate has a surface; forming field insulating regions at the surface of the semiconductor substrate; forming a gate structure insulatively disposed over the substrate and situated between the field insulating regions, the gate structure including a gate electrode; forming source/drain junction regions of a second conductivity type opposite the first conductivity type, the source/drain junction regions are formed in the substrate adjacent to the gate structure and extending from the gate structure to the field insulating regions; a channel region disposed between the source/drain regions beneath the gate structure in the substrate; a self-aligned silicide region formed on the source/drain junction regions, the silicide formed by depositing a layer of metal (preferably titanium), performing a react process and removing any unreacted metal; and forming separate electrically conductive regions (preferably comprised of CVD-WSi
x
, where x is between 2 and 3) using a nonselective conductive layer deposition process, each contacting one of the source/drain regions, and simultaneously forming another electrically conductive region from the same conductive material on the gate structure.
Another embodiment of the instant invention is a method for fabricating a semiconductor device with a self-aligned silicide region, the method comprising: providing a semiconductor substrate of a first conductivity type, the semiconductor substrate has a surface; forming field insulating regions at the surface of the semiconductor substrate; forming a gate structure insulatively disposed over the substrate and between the field insulating regions, the gate structure having a top surface and a side surface and including a gate electrode; forming a disposable structure (preferably comprising silicon nitride) overlying the gate structure, the disposable structure having a top surface and a side surface; forming side wall insulators adjacent to the gate structure and the disposable structure and extending along side surfaces of the gate structure and the disposable structure; forming source/drain junction regions of a second conductivity type opposite the first conductivity type, the source/drain junction regions formed in the substrate adjacent to the gate structure and extending from the gate structure to the field insulating regions; providing a channel region disposed between the source/drain junction regions beneath the gate structure in the substrate; selectively removing the disposable structure; providing a silicide region formed on the source/drain junction regions, the silicide formed by depositing a layer of metal (preferably comprising titanium), performing a react process and removing any unreacted metal and metal composites; forming separate electrically conductive regions by means of a nonselective conductive material layer deposition process, each contacting one of the source/drain junction regions, and simultaneously forming an electrically conductive region from the same conductive material (preferably comprised of CVD-WSi
x
, where the value of x is in between 2 and 3) on the gate structure (preferably the conductive region on the gate structure is substantially the same thickness as the disposable structure); and wherein the conductive region formed on the gate structure is located in substantially the same location as the disposable structure. In one alternative embodiment the silicide region is formed after the disposable layer is removed thereby forming the silicide layer on the gate structure and between the gate structure and the conductive region on the gate structure. In another embodiment the silicide region is formed before the disposable layer is removed thereby providing the silicide region only on the source

Affiliated with

Also associated with

Rating

High performance self-aligned silicide process for... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with High performance self-aligned silicide process for..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High performance self-aligned silicide process for... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2527271