Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-06-02
2001-08-28
Chaudhuri, Olik (Department: 2814)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C257S408000, C257S394000
Reexamination Certificate
active
06281088
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device and method of manufacturing the same, and more particularly, to a Static Random Access Memory cell capable of enhancing cell ratio and a manufacturing method thereof.
2. Description of the Related Art
A semiconductor memory device is classified into a dynamic random access memory (DRAM) and a static random access memory (SRAM) according to its method of storing data. SPAM is particular significant due to its high speed, low power consumption, and simple operation. In addition, unlike the DRAM, the SRAM has advantage of an easy design as well as not having to regularly refresh stored data.
In general, SRAM cell includes: two driving transistors which are pull-down devices; two access devices; and two pull-up devices. The SRAM cell is further classified as a full CMOS cell, a high road resistor(HRL) cell, or a thin film transistor (TFT) cell according to the type of the pull-up devices used.
The full CMOS cell utilizes a P-channel bulk MOSFET as the pull-up device. The HRL cell utilizes a polysilicon having a high resistance value as the pull-up device, and TFT cell utilizes P-channel polysilicon TFT as the pull-up device. Of the above-mentioned structures, the SRAM cell with the full CMOS cell structure has optimal operational device properties and can be fabricated with a simple process. It, however, has both NMOS and PMOS transistors in the unit cell, resulting in a large cell size. Therefore, it is applied to the memory device having a small capacitance. On the other hand, SRAM cells with the HRL cell and the TFT cell structures have relatively poor performance and is complicated in their fabrication. Because of their smaller cell size, however they are generally applied to semiconductor memory device in cases of larger capacitance.
FIG. 1
is a conventional circuit diagram of an SRAM cell with the full CMOS cell structure.
As shown in this diagram, sources S
1
and S
2
of PMOS transistors Q
1
and Q
2
for use in pull-up devices are connected to VDD. Drains D
1
and D
2
of the PMOS transistors Q
1
and Q
2
are respectively connected in series to each drains D
3
and D
4
of NMOS transistors Q
3
and Q
4
for use in pull-down devices at nodes N
1
and N
2
. Sources S
3
and S
4
of the NMOS transistors Q
3
and Q
4
are connected to VSS. Gates G
1
and G
2
of the PMOS transistors Q
1
and Q
2
are respectively connected to gates G
3
and G
4
of the NMOS transistors Q
3
and Q
4
, and these connection points thereof are respectively cross-coupled with the nodes N
1
, N
2
. In NMOS transistors Q
5
and Q
6
for use in access devices, gates G
5
and G
6
are connected to a word line W/L, sources S
5
and S
6
are respectively connected to bit lines B/L
1
and B/L
2
. Drains D
5
and DG of NMOS transistors Q
5
and Q
6
are respectively connected to the drains D
3
and D
4
of the NMOS transistors Q
3
and Q
4
at the nodes N
1
, N
2
.
In the above described SRAM cell, the NMOS transistors Q
5
and Q
6
are turned on by turning on the word line W/L, to store data in a HIGH state in the node N
1
and data in a LOW state in the node N
2
. Data in a HIGH state is inputted to the bit line B/L
1
and data in a LOW state is inputted to the bit line B/L
2
, so that the PMOS transistor Q
1
and NMOS transistor Q
4
are turned on, and PMOS transistor Q
2
and NMOS transistor Q
3
are turned off. Therefore, the node N
1
becomes a HIGH state and the node N
2
becomes a LOW state. Furthermore, although the word line W/L is turned off, the node N
2
is latched to maintain a LOW state and the node Ni is maintained at a HIGH state.. Accordingly, data is stored in the nodes N
1
and N
2
respectively.
Meanwhile, one of the factors determining the characteristics of the SRAM is the current driving capability ratio of the pull down device, otherwise known as the driving device and the access device (I
DSAT DRIVER TRANSISTOR
/I
DSAT ACCESS TRANSISTOR
), otherwise known as cell ratio. A higher cell ratio results in improved performance of the SRAM. Therefore when the current amount of the pull down device is large and the current amount access device is small, the performance of the SRAM cell is improved.
An operation of the SRAM related to the cell ratio is as follows. In case the data in a low state is stored in the node N
1
and the data in a high state is stored in the node N
2
, the voltage of the node N
1
is determined by the current amount ratio of the NMOS transistors Q
5
and Q
6
for use in access devices and the NMOS transistors Q
3
and Q
4
for use in pull down devices. Accordingly, the node N
1
is intended to maintain the low voltage with the increase of the current amount of the NMOS transistors Q
3
and Q
4
, and with the decrease of that of the NMOS transistors Q
5
and Q
6
. If so, the voltage of the node N
1
is not drastically changed from the low state when the NMOS transistors Q
5
and Q
6
are turned on during the reading operation, even though the voltage of the bit line B/L
1
is changed. In case the voltage variation of the node N
1
is small, the voltage of the cross-coupled node N
2
is still maintained in the high state.
Therefore, conventionally, the cell ratio is controlled in a manner wherein width of the NMOS transistor for use in access device is reduced and its length is increased to thereby reduce its the current amount, and width of the NMOS transistor for use in pull-down device is increased and its length is reduced to thereby increase its the current amount. The width and length of the transistor, however, cannot be reduced below a predetermined level, and therefore there is a restriction in reducing the size of the cell to enhance the cell ratio.
SUMMARY OF THE INVENTION
Accordingly, an object of the present invention is to provide an SRAM cell and manufacturing method of the same, which selectively reduce the concentration of impurity ion of source/drain regions of an access devices, and increases a parasitic resistance of the access devices, thereby reducing the current amount of access devices and enhancing the cell ratio of the SPAM cell.
In accordance with one embodiment, there is provided a SRAM cell including pull down devices, access devices and pull up devices each having source and drain regions with LDD structure, the source and drain regions of the access device having; N
+
source and drain regions; N
−
source and drain regions formed under the N
+
source and drain regions; and a P
−
impurity region wherein a predetermined portion thereof, is overlapped with the N
−
source and drain regions.
In this embodiment, the concentration of N type impurity of a region wherein said P
−
impurity region and said N
−
source and drain regions of said access devices are overlapped, is lower than that of said N
−
source and drain regions.
There is also provided a method of manufacturing an SPAM celt having pull down devices, access devices and pull up devices, the manufacturing method including the steps of: providing a semiconductor substrate of which an active region is defined and a gate insulating layer and a gates are formed on thereof; respectively forming N
−
source and drain regions in the substrate of both sides of gates of the pull down devices region and the access devices region; and forming P
−
impurity regions on predetermined portions of the N
−
source and drain regions of the access devices region.
In this embodiment, the impurity concentration of the P
−
impurity regions is lower than that of the N
−
source and drain regions.
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patent: 5396098 (1995-03-01), Kim et al.
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patent: 5594267 (1997-01-01), Ema et al.
patent: 5629546 (1997-05-01), Wu et al.
patent: 5780902 (1998-07-01), Komuro
patent
Chaudhuri Olik
Hyundai Electronics Industries Co,. Ltd.
Weiss Howard
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