Method of forming a contact using a sacrificial spacer

Details Method of forming a contact using a sacrificial spacer Method of forming a contact using a sacrificial spacer

1998-10-16

2001-09-04

Whitehead, Jr., Carl (Department: 2822)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S397000, C438S626000, C438S629000, C438S632000

Reexamination Certificate

active

06284641

ABSTRACT:

BACKGROUND OF THE INVENTION
1. The Field of the Invention
The present invention relates to the formation of a depression in a semiconductor structure. More particularly, the present invention relates to a method of forming a sacrificial plug in a semiconductor structure during a damascene process. In particular, the present invention relates to a method of forming a sacrificial nitride spacer as part of the formation of a contact to a polysilicon plug that makes contact to a semiconductive substrate. The inventive method of forming the sacrificial spacer also provides an advantage of being self-aligned to the underlying polysilicon plug that is to be contacted.
2. The Relevant Technology
In the microelectronics industry, a substrate refers to one or more semiconductor layers or structures which include active or operable portions of semiconductor devices. In the context of this document, the term “semiconductive substrate” is defined to mean any construction comprising semiconductive material, including but not limited to bulk semiconductive material such as a semiconductive wafer, either alone or in assemblies comprising other materials thereon, and semiconductive material layers, either alone or in assemblies comprising other materials. The term substrate refers to any supporting structure including but not limited to the semiconductive substrates described above.
In the fabrication of semiconductor devices, metal contacts are formed over semiconductor substrates that have been processed to form devices connected to each other to form integrated circuits. In particular, the devices are connected with aluminum and aluminum alloys lines that have been deposited into vias and other recesses such as trenches and contact corridors. This method is used generally in the industry. However, as devices have been miniaturized, due to a higher device density on a semiconductor substrate and a smaller device, the openings to be filled have smaller cross-sectional “footprints”.
Typically, contacts have cross-sectional footprints of about 0.35 microns or smaller. The alignment of a composite contact with a footprint of about 0.35 microns is problematic, and fabrication yield with such a process prerequisite may be unacceptably low due to misalignment. In addition to the problem of sub-micron misalignment of a composite contact, an increased resistivity is caused due to a physical seam between two discrete sections of the contact.
While the aluminum in the contact and an active area in a semiconductor substrate must be electrically connected, it has become useful to use intermediate layers to provide better electrical connection to the semiconductive substrate, and to provide a metallurgical barrier between the active area and the aluminum to prevent spiking of the aluminum into the active area. Spiking can interfere with the performance and reliability of the integrated circuit.
Conventionally, one method which has been used to accomplish the metallurgical barrier has been to form a layer of titanium over a semiconductor substrate at the interconnect-exposed site, to form a titanium silicide barrier layer at the exposed site, and in the presence of nitrogen, to form a titanium silicide/titanium nitride composite layer substantially from the titanium layer. Another solution has been to form the titanium silicide barrier layer first and then to sputter additional titanium nitride over the titanium silicide or titanium silicide/titanium nitride layer. In this way, a sufficient thickness of titanium nitride may be formed to provide a desired thickness in the metallurgical barrier.
Typically, in order to form a composite contact consisting of, for example, a metallization trench above a polysilicon plug that contacts a semiconductive substrate or a metallization trench that contacts the polysilicon plug, two photolithography steps are carried out.
FIG. 1
illustrates a first step in the two-step photolithography process, wherein a semiconductor structure
10
includes a semiconductive substrate
12
with raised structures thereon such as a gate stack
14
. Gate stack
14
may be covered with a dielectric layer
16
such as an oxide, for example, boro phospho silicate glass (BPSG) and the like. Typically, but not necessarily, an interlayer dielectric (ILD)
18
may be formed upon dielectric layer
16
.
A first aspect of forming a contact to semiconductive substrate
12
is carried out by patterning a first masking layer
20
and carrying out an anisotropic etch such as to form a first recess
22
through interlayer dielectric
18
. Where interlayer dielectric
18
is not present, first recess
22
forms to a limited depth within dielectric layer
16
but first recess
22
does not penetrate substantially to expose semiconductive substrate
12
. First masking layer
20
is then removed.
Following formation of first recess
22
, a second masking layer
24
seen in
FIG. 2
is formed upon semiconductor structure
10
and patterned to be substantially aligned with first recess
22
in preparation for a second etch. This second etch is an aspect of a dual-damascene etch process that is used to form a contact corridor. The second etch is carried out to sufficiently penetrate through dielectric layer
16
and to stop on semiconductive substrate
12
so as to form a second recess
26
. The dual-damascene feature can be seen in
FIG. 2
wherein interlayer dielectric
18
has an ILD sidewall
30
and dielectric layer
16
has a dielectric layer sidewall
32
.
Forming a dual-damascene structure for a contact according to the prior art includes the problem of a dual or single misalignment during patterning of either first masking layer
20
or second masking layer
24
. Where patterning of either first masking layer
20
or second masking layer
24
is misaligned, etching of either first recess
22
or second recess
26
may cause destructive etching into gate stack
14
. Etching into gate stack
14
, followed by filling with an electrically-conductive material will likely cause shorting between the electrically conductive material and the electrically conductive portion of gate stack
14
. Where first recess
22
may be misaligned, formation of second recess
26
may require penetration both through dielectric layer
16
but also through interlayer dielectric
18
such that the total effect of etching may not penetrate dielectric layer
16
sufficiently to expose semiconductive substrate
12
to a “footprint” area sufficient for a functioning contact. Where semiconductive substrate
12
is not exposed, an inadequate contact may be formed within second recess
26
.
Another example of forming a composite contact includes forming a first recess that is substantially above a polysilicon plug. Forming a contact hole within the recess exposes an upper surface of the polysilicon plug. Formation of first recess
22
is done through interlayer dielectric
18
when used in a process to form a composite contact. The composite contact formation process includes a polysilicon plug (not shown) and forming first recess
22
to a limited depth within dielectric layer
16
. However, first recess
22
does not penetrate substantially to expose the polysilicon plug.
FIGS. 3-6
illustrate a prior art process of forming a dual-damascene contact structure to a polysilicon plug, and also show some of the disadvantages of prior art. In
FIG. 3
, semiconductor structure
10
has been processed to form a contact plug
36
and a storage node
38
by a uniform etchback of a polysilicon film that has been deposited over and around sacrificial spacers
40
.
In
FIG. 4
, further processing has been carried out, wherein a cell dielectric
42
and a cell plate layer
44
have been substantially conformably deposited upon storage node
38
and contact plug
36
. It can also be seen that a dielectric film
46
, an optional nitride layer
48
, and second masking layer
24
have been formed upon semiconductor structure
10
, whereby second masking layer
24
indicates with dashed lines an etch footprint that will be formed during an etch to

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