Static information storage and retrieval – Systems using particular element – Ferroelectric
Reexamination Certificate
1999-12-14
2001-03-20
Elms, Richard (Department: 2824)
Static information storage and retrieval
Systems using particular element
Ferroelectric
C365S065000, C257S295000
Reexamination Certificate
active
06205048
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, a method for manufacturing the same, a memory circuit, and a method for driving the same, and more particularly, to a single transistor cell, a method for manufacturing the same, a memory circuit composed of the single transistor cells, and a method for driving the memory circuit.
2. Description of the Related Art
A ferroelectric material is a dielectric material in which polarization generated by an external electric field remains partially after removing the external electric field, and the polarization direction can be changed by changing the direction of the external electric field.
Memory devices manufactured using a ferroelectric thin film may be categorized into two types.
The first type of device is a destructive read out (DRO) type memory device, which means that when data is read out, the data is lost from the memory and must be written again. The device is constituted with a capacitor which is manufactured using a ferroelectric thin film dielectric, and a transistor which is used to read or write signals of two directions stored in the capacitor. Here, the memory device is commonly called a ferroelectric random access memory (FRAM), and the driving principle thereof is similar to a dynamic random access memory (DRAM). However, unlike the DRAM, the FRAM requires no refresh and is a non-volatile memory which keeps stored information even when the power supply is turned off.
The second type of device is a non-destructive read out (NDRO) ferroelectric memory device which reads stored information without destruction, unlike the DRO memory device. The device is obtained by forming a ferroelectric capacitor on the gate electrode of a transistor, and operates by determining whether a channel exists in a silicon surface under a gate oxide layer along a polarization direction of the ferroelectric capacitor. For instance, it is recognized that if a channel exists, 1 is written, and if not, 0 is written.
A memory cell including only a single transistor without a capacitor, unlike the DRAM or FRAM, would be advantageous for integration, but would require an access for selecting a cell or a selection transistor in order to perform random access.
No method for exactly realizing an array of cells each formed of only one transistor of an NDRO type has been disclosed. However, a similar SFRAM is disclosed in U.S. Pat. No. 5,070,385 “Ferroelectric non-volatile variable resistive element” by Evans, Jr., Joseph T. and Bullington, Jeff A.
FIG. 1
is a sectional view of a conventional SFRAM, disclosed in the above patent.
In
FIG. 1
, reference numeral
10
indicates a gate, which is actually part of, a word line, reference numeral
12
indicates a ferroelectric layer, reference numeral
14
indicates a channel region, reference numeral
16
indicates a drain, reference numeral
18
indicates a source, reference numeral
20
indicates an interdielectric layer, reference numeral
22
indicates a first metal electrode, and reference numeral
24
indicates a second metal electrode.
The SFRAM of
FIG. 1
is a thin film transistor (TFT). The word line
10
is formed on a semiconductor substrate (not shown), and the ferroelectric layer
12
is formed on the word line
10
. Here, an oxide layer (not shown) is interposed between the word line
10
and the semiconductor substrate. The drain
16
is formed on a left semiconductor layer around the word line
10
, and the source
18
is formed on the right semiconductor layer. The channel region
14
is formed between the drain
16
and the source
18
above the word line
10
.
When a predetermined voltage is applied to the word line
10
, the spontaneous polarization is induced in the ferroelectric layer
12
, and thus a conductive channel is formed or not formed in the channel region
14
.
For instance, if the source and drain are doped with an N-type impurity, and by a drive method “1” or “0” is written to a cell transistor, then “1” indicates the state in which the conductive channel is formed in the channel region, and “0” indicates the state in which no conductive channel is formed. When a positive voltage (+V) is applied to the word line
10
, N-type ions are accumulated in the channel region
14
due to the polarization of the ferroelectric layer
12
, so that the conductive channel is formed, to thereby write “1” in the cell transistor. When a negative voltage (−V) is applied to the word line
10
, P-type ions are accumulated in the channel region
14
due to the polarization of the ferro dielectric layer
12
, so that a non-conductive channel is formed, to thereby write “0” in the cell transistor.
Meanwhile, in order to read the data stored in the cell transistor, if +V is applied to the second metal electrode
24
while the conductive channel is formed in the channel region
14
, i.e., “1” is written, current passes through the first metal electrode
22
, and if a non-conductive channel is formed in the channel region
14
, i.e., “0” is written, current does not pass through the first metal electrode
22
. Thus, the current passing through the first metal electrode
22
is measured, to thereby read the cell transistor of “1” or “0”.
In the conventional SFRAM, read and write are performed by normal drive of the unit cell. However, in order to read or write information in an arbitrary unit cell, each cell requires a further two access transistors, which prevents high integration density for the memory device.
SUMMARY OF THE INVENTION
It is an objective of the present invention to provide a single transistor cell including a unit cell formed of one transistor, capable of random access of the unit cell.
It is another objective of the present invention to provide a method of manufacturing the single transistor cell.
It is still another objective of the present invention to provide a memory circuit formed of single transistor cells, in which a unit cell is formed of one transistor, and which can randomly access the unit cells.
It is yet another objective of the present invention to provide a method for driving the memory circuit.
Accordingly, to achieve the first objective, a single transistor cell according to the present invention comprises an island type semiconductor layer as an active region formed on a ferroelectric layer, a word line crossing the semiconductor layer, a source formed on the semiconductor layer one side of on the word line, and a drain formed on the semiconductor layer on the other side of the word line, a plate line formed below the ferroelectric layer to face the word line, intersecting the word line, a drive line connected to the source, and a bit line connected to the drain.
Here, the plate line is formed of platinum, and the ferroelectric line is formed of one selected from the group consisting of PZT, PLZT, PNZT, PbTiO3 and Y1. the semiconductor layer is formed of an oxide such as SnO
2
. The word line is formed of a material having a high work function, to reduce leakage current. Also, the word line is formed of either polysilicon doped with impurities or aluminum.
To achieve the second objective, a method for manufacturing a single transistor cell according to the present invention comprises (a) forming a rectangular plate line extending in a first direction, on a semiconductor substrate, (b) forming a rectangular ferroelectric line extending in a second direction perpendicular to the first direction to intersect the plate line, on the resultant structure where the plate line is formed, (c) forming an island type semiconductor layer on the ferroelectric line in a region where the ferroelectric line overlaps the plate line, and (d) forming a rectangular word line extending in the second direction to cross the semiconductor layer.
A reaction preventing layer is formed before forming the plate line, to suppress reaction of the semiconductor substrate with the ferroelectric line. The reaction preventing layer is formed of TiO
2
.
Forming the plate line comprises the substeps of depositin
Elms Richard
Jones Volentine, L.L.C.
Nguyen Tuan T.
Samsung Electronics Co,. Ltd.
LandOfFree
Single transistor cell, method for manufacturing the same,... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Single transistor cell, method for manufacturing the same,..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Single transistor cell, method for manufacturing the same,... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2523619