Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-11-12
2001-06-19
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S266000
Reexamination Certificate
active
06248623
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method for manufacturing a semiconductor. More particularly, the present invention relates to a method for manufacturing an embedded memory with different spacer widths.
2. Description of Related Art
In order to decrease the semiconductor manufacturing cost and simplify the fabrication procedures, a method for putting memory and logic devices together on a semiconductor chip is developed.
Typically, an embedded DRAM comprises a memory device region and a logic circuit region. The memory devices and the logic devices are together formed on the same wafer. The benefits of the embedded DRAM include high yield, short cycle time and low manufacturing cost. However, the specific requirements of the memory devices and the logic devices are different from each other, so that the procedures for manufacturing the embedded DRAM must be modified to fit those requirements. Taking the logic device as an example, the logic device requires a relatively high operation rate. Therefore, it is necessary to form a silicide layer on the surface of the source/drain region in the logic device. However, the formation of the silicide layer on the surface of the source/drain region in the memory device leads to a leakage issue for the capacitor. Hence, before forming a silicide layer on the surface of the source/drain region, it is necessary to additionally form a protective layer such as a silicon nitride layer over the memory device region in the embedded DRAM. The protective layer is then removed after the silicide layer is formed.
Additionally, with the increase in the integration, the line width and the space between the gate structures are decreased. The spacer width of the spacer formed on the sidewall of the gate structure must be decreased to provide enough space for forming a bit line contact or a storage node contact. However, the space width of the logic device is not decreased when decreasing the size of the embedded DRAM because the logic device with a high performance must fit the requirement of high operation rate and large process window. Therefore, it is difficult to simultaneously form a memory device and a logic device in an embedded DRAM.
SUMMARY OF THE INVENTION
The invention provides a method of manufacturing an embedded memory with different spacer widths. A substrate having a memory cell region and a logic circuit region is provided. A plurality of first gate structures and a plurality of second gate structures are respectively formed on the substrate in the memory cell region and the logic circuit region. Every space between the first gate structures is smaller than that between the second gate structures. A first spacer is formed over a sidewall of each first gate structure and over a sidewall of each second gate structure. Several lightly doped drain regions are formed in the substrate exposed by the first spacers and the second gate structures in the logic circuit region. A second spacer is formed on each first spacer in the logic circuit region and a silicide block is simultaneously formed to fill spacers between the first gate structures in the memory cell region. A source/drain is formed in the substrate exposed by the second spacers, the first spacers and the second gate structures in the logic circuit region. A silicide layer is formed on the substrate exposed by the second spacers, the first spacers and the second gate structures in the logic circuit region.
In the invention, the spacers with different widths are formed by a two-step formation process to simultaneously meet the spacer width requirements of the logic circuit device and the memory device. Therefore, the operation performances of the logic circuit device and the memory device can be greatly improved.
Additionally, because the silicide block formed to fill the spaces between the first gate structures can protect the memory cell region from forming the silicide layer, the silicide layer is merely formed in the logic circuit region. Hence, the operation rate of the logic circuit device is increased and the subsequently formed capacitor in the memory cell region possesses a relatively long refresh cycle.
Furthermore, the first spacers are used as lightly doped drain offset spacers, so that the overlay capacitor between the source/drain regions and the second gate structures is reduced. Therefore, the operation rate of the logic circuit device is increased and the hot carrier effect can be avoided.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5899722 (1999-05-01), Huang
patent: 5972764 (1999-10-01), Huang et al.
patent: 6017790 (2000-01-01), Liou et al.
patent: 6020242 (2000-02-01), Tsai et al.
patent: 6030867 (2000-02-01), Chien et al.
Chien Sun-Chieh
Kuo Chien-Li
Nelms David
Nhu David
Thomas Kayden Horstemeyer & Risley LLP
United Microelectronics Corp.
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