Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1998-05-12
2001-04-03
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S257000, C438S281000, C438S592000, C438S664000
Reexamination Certificate
active
06211074
ABSTRACT:
TECHNICAL FIELD
The present invention relates to semiconductor devices and manufacturing processes, and more particularly to methods and arrangements associated with the formation of silicide layers in non-volatile memory semiconductor devices.
BACKGROUND ART
A continuing trend in semiconductor technology is to build integrated circuits with more and/or faster semiconductor devices. The drive toward this ultra large-scale integration (ULSI) has resulted in continued shrinking of device and circuit features. As the devices and features shrink, new problems are discovered that require new methods of fabrication and/or new arrangements.
A flash or block erase Electrically Erasable Programmable Read Only Memory (flash EEPROM) semiconductor memory includes an array of memory cells that can be independently programmed and read. The size of each memory cell, and therefore the memory array, is made small by omitting select transistors that would enable the cells to be erased independently. The array of memory cells is typically aligned along a bit line and a word line and erased together as a block. An example of a memory of this type includes individual metal oxide semiconductor (MOS) memory cells, each of which includes a source, drain, floating gate, and control gate to which various voltages are applied to program the cell with a binary 1 or 0. Each memory cell can be read by addressing it via the appropriate word and bit lies.
An exemplary memory cell
8
is depicted in
FIG. 1
a.
As shown, memory cell
8
is viewed in a cross-section through the bit line. Memory cell
8
includes a doped substrate
12
having a top surface
11
, and within which a source
13
a
and a drain
13
b
have been formed by selectively doping regions of substrate
12
. A tunnel oxide
15
separates a floating gate
16
from substrate
12
. An interpoly dielectric layer
24
separates floating gate
16
from a control gate
26
. Floating gate
16
and control gate
26
are each electrically conductive and typically formed of polysilicon.
On top of control gate
26
is a silicide layer
28
, which acts to increase the electrical conductivity of control gate
26
. Silicide layer
28
is typically a tungsten silicide (e.g., WSi
2
), that is formed on top of control gate
26
prior to patterning, using conventional deposition and annealing processes.
As known to those skilled in the art, memory cell
8
can be programmed, for example, by applying an appropriate programming voltage to control gate
26
. Similarly, memory cell
8
can be erased, for example, by applying an appropriate erasure voltage to source
13
a.
When programmed, floating gate
16
will have a charge corresponding to either a binary 1 or 0. By way of example, floating gate
16
can be programmed to a binary 1 by applying a programming voltage to control gate
26
, which causes an electrical charge to build up on floating gate
16
. If floating gate
16
does not contain a threshold level of electrical charge, then floating gate
16
represents a binary 0. During erasure, the charge is removed from floating gate
16
by way of the erasure voltage applied to source
13
a.
FIG. 1
b
depicts a cross-section of several adjacent memory cells from the perspective of a cross-section through the word line (i.e., from perspective A, as referenced in
FIG. 1
a
). In FIG.
1
b,
the cross-section reveals that individual memory cells are separated by isolating regions of silicon dioxide formed on substrate
12
. For example,
FIG. 1
b
shows a portion of a floating gate
16
a
associated with a first memory cell, a floating gate
16
b
associated with a second memory cell, and a floating gate
16
c
associated with a third memory cell. Floating gate
16
a
is physically separated and electrically isolated from floating gate
16
b
by a field oxide (FOX)
14
a.
Floating gate
16
b
is separated from floating gate
16
c
by a field oxide
14
b.
Floating gates
16
a,
16
b,
and
16
c
are typically formed by selectively patterning a single conformal layer of polysilicon that was deposited over the exposed portions of substrate
12
, tunnel oxide
15
, and field oxides
14
a-b.
Interpoly dielectric layer
24
has been conformally deposited over the exposed portions of floating gates
16
a-c
and field oxides
14
a-b.
Interpoly dielectric layer
24
isolates floating gates
16
a-c
from the next conformal layer which is typically a polysilicon layer that is patterned (e.g., along the bit line) to form control gate
26
. Interpoly dielectric layer
24
typically includes a plurality of films, such as, for example, a bottom film, of silicon dioxide, a middle film of silicon nitride, and a top film of silicon dioxide. This type of interpoly dielectric layer is commonly referred to as an oxide-nitride-oxide (ONO) layer.
The continued shrinking of the memory cells, and in particular the features depicted in the memory cells of
FIGS. 1
a-b,
places a burden on the fabrication process to deposit/form the floating, gate
16
and control gate
26
without creating deleterious effects within the memory cell. Of particular concern, caused by the shrinking dimensions, is the need to provide adequate electrical isolation between each of the floating gates
16
a-c,
and between each of the floating gates
16
a-c
and control gate
26
, while also providing an adequately arranged floating/control gate configuration. For example, one of the problems that has been encountered with reduced-size semiconductor devices is the tendency for deleterious cracks to form due to stress within control gate structures that employ silicide layer
28
.
SUMMARY OF THE INVENTION
These needs and others are met by the present invention, which provides methods and arrangements that increase the process control during the fabrication of semiconductor devices, and in particular, during the formation of a silicide layer and cap layer within a control gate configuration in a non-volatile memory semiconductor device.
In accordance with one aspect of the present invention, it has been found that in certain semiconductor arrangements, the topology created by the space between adjacent floating gates cars be so severe in shape (e.g., deep and narrow) that the silicide layer formed on the overlying control gate often contains significant depressions over the space. These significant depressions can lead to cracks in the silicide layer during subsequent thermal processing during the fabrication of the semiconductor device, which tends to stress and/or alter the silicide layer.
In accordance with one aspect of the present invention, the amount of stress in the silicide layer is reduced by altering the process by which the silicide layer is formed and/or the subsequent process by which an overlying cap layer is formed on the silicide layer. For example, instead of a conventional polysilicon cap layer that requires a high deposition temperature of about 680° C., in accord with certain aspects of the present invention an amorphous polysilicon cap layer that only requires a deposition temperature of about 500° C. is employed to reduce the amount of thermally induced stress within the silicide layer.
Thus, in accordance with certain embodiments of the present invention, a method for forming a silicide layer and a cap layer in a semiconductor device is provided. The method includes depositing a silicide layer on a first layer at a first deposition temperature, and depositing a cap layer on the silicide layer at a second deposition temperature, wherein a temperature difference between the first deposition temperature and the second deposition temperature is less than about 250° C. Having a reduced temperature difference, for example, less than about 250° C., has been found to significantly reduce cracking of the silicide layer.
For example, in accordance with certain embodiments of the present invention, the step of depositing the silicide layer includes forming tungsten silicide on the first layer using chemical vapor deposition (CVD) techniques and reacting SiH
4
and WF
6
at a temperature at betwe
Huang Richard J.
Morales Guarionex
Advanced Micro Devices , Inc.
Bowers Charles
Nguyen Thanh
LandOfFree
Methods and arrangements for reducing stress and preventing... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Methods and arrangements for reducing stress and preventing..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methods and arrangements for reducing stress and preventing... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2522687