Method for forming flash memory cell

Details Method for forming flash memory cell Method for forming flash memory cell

1998-12-30

2001-05-22

Booth, Richard (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S564000

Reexamination Certificate

active

06235582

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application Ser. No. 87117658, filed Oct. 26, 1998, the full disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates in general to a method for forming a non-volatile memory device, and more specifically relates to a method for forming a flash memory.
2. Description of Related Art
Electrically erasable and programmable read only memory (EEPROM) is a widely used memory device in personal computers and electric devices. A conventional EEPROM has a floating gate to accomplish the function of erasing and programming the EEPROM. However, the EEPROM has a low access speed problem; typical access speed is about 150 ns to 200 ns. In response, Intel Corp. has developed a new EEPROM called flash memory, which has a high access speed about 70 ns to 80 ns.
FIGS. 1
to
3
show top views of a portion of a manufacturing process for forming a flash memory cell by a conventional method. For clear description, cross-sectional views with respect to line I—I in individual
FIGS. 1
to
3
are respectively shown in
FIGS. 1A
to
3
A.
FIG. 3B
shows a cross-sectional view with respect to line II—II in FIG.
3
.
Referring to FIG.
1
and
FIG. 1A
, a number of block field oxides
102
are formed by shallow trench isolation on a silicon substrate
100
, by which column active regions
103
having a width
132
and row active regions
104
are defined.
Referring to FIG.
2
and
FIG. 2A
, a mask layer
106
which has openings
108
,
109
with width
134
to expose the column active regions
103
and a portion of row active regions
104
is deposited on the substrate. An ion implantation process using the mask layer
106
as an etching mask is performed to form buried bit lines
114
,
116
which also serve as the source/drain regions of the flash memory, and a channel region
110
is formed between the source/drain regions. It should be noted that the opening width
134
of the mask layer
106
must be greater than the width
132
of the column active regions
103
so that the buried bit lines
114
,
116
can self-align to the column active regions
103
and have good conductive property. However, increasing the opening width
134
increases the width of buried bit lines
114
,
116
so that the channel region length
130
is reduced which causes a short channel effect.
Referring to FIG.
3
and
FIG. 3A
, a tunneling oxide
118
is deposited on the substrate
100
by thermal oxidation. A polysilicon floating gate
120
, dielectric layer
122
and polysilicon controlling gate are sequentially formed on the tunneling oxide
118
to form a gate structure
128
of the flash memory.
FIG. 3B
shows a cross-sectional view with respect to line II—II in FIG.
3
. Sharp corners
129
are formed at the boundary between the block field oxide
102
and column active regions
114
,
116
that usually cause a leakage current. The leakage current will damage the flash memory so that the yield is reduced.
According to the forging description, in order to solve the self-alignment problem, the buried bit line width must be greater than the column active region width, which reduces the channel length. In order not to reduce the channel length, it is necessary to increase the active region area, which will decrease the device integration. Furthermore, the block field oxide usually causes a leakage current which damages the flash memory so that the yield is reduced.
SUMMARY OF THE INVENTION
According to the foregoing description, an object of this invention is to provide a method for forming a flash memory cell, by which the source/drain region width does not restrict to the buried bit line alignment problem and the device integration increases.
Another object of this invention is to provide a method for forming a flash memory cell, by which a leakage current phenomenon is reduced and the yield is increased.
According to the objects mentioned above, a method for forming a flash memory cell is provided. A first and a second patterned conductive layers, each respectively having a dopant, are formed on a substrate. A portion of the dopant within the first patterned conductive layer is driven into the substrate to form a first source/drain region, and a portion of the dopant within the second patterned conductive layer is driven into the substrate to form a second source/drain region, wherein a channel region is formed between the first and the second source/drain regions. A gate structure of the flash memory cell is formed on the channel region. The gate comprises a tunneling oxide, a floating gate, a dielectric layer and a controlling gate which are formed on the channel region.


REFERENCES:
patent: 4124934 (1978-11-01), De Brebisson
patent: 5597741 (1997-01-01), Sakamoto et al.
patent: 5753551 (1998-05-01), Sung
patent: 5773346 (1998-06-01), Manning
patent: 6040221 (2000-03-01), Manning

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