Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-01-13
2001-05-08
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S637000, C438S696000
Reexamination Certificate
active
06228762
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of electronics and more particularly to methods of forming contact holes for electronic devices and related structures.
Background of the Invention
FIG. 1
is a cross-sectional view showing a storage node contact of an ideal semiconductor memory device.
Referring to
FIG. 1
, a storage node contact of an ideal semiconductor memory device is described as having a storage node contact hole
20
a
which is formed so as not to expose a bit line
18
within insulating layer
16
b
. In detail, a device isolation layer
12
is formed to define active and inactive regions on a semiconductor substrate
10
. The device isolation layer
12
can be a shallow trench isolation layer. A contact pad
14
is formed to be electrically connected to the active region of the semiconductor substrate
10
. First and second insulating layers
16
a
and
16
b
are sequentially formed over the semiconductor substrate
10
, including the contact pad
14
. A bit line
18
is located between the first and second insulating layers
16
a
and
16
b.
The second and first insulating layers
16
b
and
16
a
are sequentially etched to form a storage node contact hole
20
a
which exposes a portion of the contact pad
14
. An insulating spacer
22
a
is formed on sidewalls of the storage node contact hole
20
a
. A storage node
24
is formed by filling the storage node contact hole
20
a
with a conductive layer such as a layer of polysilicon.
FIGS. 2 and 3
are cross-sectional views showing storage node contacts of a conventional semiconductor memory device.
Referring to
FIG. 2
, portions of the bit lines
18
on both sides of the contact hole
20
b
may be exposed if the size of the storage node contact hole
20
b
increases due to overexposure or overetching when forming the storage node contact hole. If an insulating spacer
22
b
and then a storage node
24
are formed as shown in
FIG. 2
, a short circuit between the exposed portion of the bit line
18
and the storage node
24
may result (reference number
25
).
Referring to
FIG. 3
, a portion of the bit line
18
on one sidewall of the contact hole
20
c
may be exposed due to misalignment when the storage node contact hole
20
c
is formed. If an insulating spacer
22
c
and then a storage node
24
are formed as shown in
FIG. 3
, a short-circuit between the exposed portion of the bit line
18
and the storage node
24
may be generated (reference number
25
).
The above-mentioned short-circuit conditions resulting from the exposed portions of the bit line
18
may become a severe problem as more highly integrated DRAMS are developed. In particular, problems related to the short-circuit conditions discussed above may become more severe as design rules of less than 0.25 &mgr;m are developed and used.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide improved methods of forming contact holes.
It is another object of the present invention to provide methods for forming semiconductor memory devices capable of reducing short-circuits between bit lines and storage node electrodes when forming storage node contacts.
These and other objects are provided according to the present invention by forming a first insulating layer on a substrate, forming a patterned conductive layer on the first insulating layer, and forming a second insulating layer on the first insulating layer and on the conductive line. A contact hole is formed through the first and second insulating layers exposing a portion of the substrate and/or a portion of the conductive layer so that sidewalls of the contact hole have a smooth profile through the first and second insulating layers. An insulating spacer is then formed on the contact hole sidewalls having the smooth profile, and a conductive via can then be formed filling the contact hole. By providing the smooth profile, the insulating spacer can more effectively separate the patterned conductive layer and other conductive layers so that short-circuits therebetween can be reduced.
In particular, the step of forming the patterned conductive layer can include forming a polysilicon layer on the first insulating layer, forming a tungsten silicide layer on the polysilicon layer, and forming an anti-reflective coating (ARC) layer on the tungsten silicide layer. In addition, the step of forming the insulating spacer can be preceded by annealing the first and second insulating layers and the patterned conductive layer at a temperature in the range of 400° C. to 800° C. The anneal can reduce projections into the contact hole resulting from reactions at the interface between the anti-reflective coating layer and the tungsten silicide layer. The anti-reflective coating (ARC) layer can be a layer of a material such as silicon nitride (SiN) or silicon oxynitride (SiON).
Moreover, the methods of the present invention can be used to provide storage node contact holes for Dynamic Random Access Memory (DRAM) devices. In particular, the patterned conductive layer can be a bit line. In addition, a conductive via can be formed in the contact hole, a first capacitor electrode can be formed on the conductive via opposite the substrate, a capacitor dielectric layer can be formed on the first capacitor electrode opposite the substrate, and a second capacitor electrode can be formed on the capacitor dielectric layer opposite the first capacitor electrode.
According to a particular aspect of the invention, the step of forming the contact hole can include forming a preliminary contact hole through the first and second insulating layers wherein a surface portion of the patterned conductive layer opposite the substrate and a sidewall of the patterned conductive layer are exposed by the preliminary contact hole so that a step is formed in a sidewall of the preliminary contact hole. In addition, the exposed portions of the patterned conductive layer can be etched to reduce the step thereby providing the contact hole sidewalls having the smooth profile.
REFERENCES:
patent: 5500080 (1996-03-01), Choi
patent: 5576242 (1996-11-01), Liu
patent: 5930668 (1999-07-01), Gardner
Berezny Nema
Bowers Charles
Myers Bigel & Sibley & Sajovec
Samsung Electronics Co,. Ltd.
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