Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-12-16
2001-08-07
Chaudhuri, Olik (Department: 2814)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S248000, C438S386000
Reexamination Certificate
active
06271080
ABSTRACT:
DESCRIPTION
1. Field of the Invention
The present invention relates to semiconductor memory cells, and more particular to a planar metal oxide semiconductor field effect transistor (MOSFET) dynamic random access memory (DRAM) cell in which the wordline gate conductor to storage trench overlay sensitivity problem typically present in prior art memory cells has been eliminated.
2. Background of the Invention
As the minimum feature size and cell architecture, i.e., number of squares, are scaled down, robust design points for dynamic random access memory (DRAM) cells utilizing metal oxide semiconductor field effect transistors (MOSFETS) and deep trench storage capacitors (also referred to herein as trench capacitors) are increasingly difficult to achieve. Scalability of the planar MOSFET in this environment is severely limited by the overlay tolerance between the wordline gate conductor, i.e., gate conductor, and the trench storage capacitor. This overlay sensitivity is exacerbated by the extent of the buried-strap outdiffusion.
One manifestation of the scalability difficulties of planar DRAM MOSFETs is degradation of the retention time tail, due to increased junction leakage resulting from very high channel doping concentrations required to suppress short-channel effects. These short channel effects (often referred to as drain induced barrier lowering (DIBL)) are greatly amplified by the encroachment of the deep-strap outdiffusion upon the array MOSFET. Because of the overlay variation between the wordline gate conductor and the deep storage trench, the distance between the edge of the buried-strap outdiffusion and the edge of the wordline gate conductor may typically vary by as much as ±30-50% of the design distance.
To guard against excessive off-current when the buried strap is close to the array MOSFET, the channel doping concentration of the array MOSFET must be elevated to levels which result in increased junction leakage. Increased junction leakage is a defect mechanism activated by the increased electrical fields associated with high channel doping. It is thus essential that the overlay variation between the wordline gate conductor and the deep storage trench be very tightly controlled.
For 6F
2
and 7F
2
planar MOSFET cells, the above-mentioned effect of wordline gate conductor and deep trench overlay tolerance is amplified relative to the 8F
2
layout; the channel length is determined by the distance between the buried-strap outdiffusion and bitline diffusion, instead of the gate conductor.
In view of the above mentioned drawback with prior art memory cell structures, there is a need for fabricating a memory cell structure (8F
2
and sub-8F
2
) that is free of wordline gate conductor to storage trench overlay sensitivity.
SUMMARY OF THE INVENTION
One object of the present invention is to provide a method of fabricating a semiconductor memory cell in which the wordline gate conductor to storage trench overlay sensitivity problem has been substantially eliminated.
Another object of the present invention is to provide a method in which precise spacing of the storage trench and adjacent wordline gate conductor of the memory cell is achieved using a single mask.
A still further object of the present invention is to provide a method which is capable of fabricating 8F
2
and sub-8F
2
memory cells.
A yet further object of the present invention is to provide a method wherein the overlay sensitivity problem is substantially eliminated and the concentration of the dopant used in forming the channel of the structure need not be increased.
These and other objects and advantages can be achieved in the present invention by utilizing the inventive method which is capable of producing a planar MOSFET trench DRAM cell that is immune to wordline gate conductor to trench capacitor overlay tolerance.
In accordance with one aspect of the present invention, a method of fabricating a planar MOSFET trench DRAM cell that has a distance between wordline gate conductor and storage trench which is entirely independent of overlay is provided. Specifically, the present invention provides a method of forming a memory cell in a semiconductor substrate, said memory cell comprising trench capacitors, transfer transistors, bitlines and wordlines, said method comprising:
(a) forming a stack of at least four material layers on a surface of a semiconductor substrate, wherein at least two of said material layers of said stack are selectively etchable relative to each other;
(b) patternwise etching through said stack to define a critical pattern of remaining stack and spaces where said semiconductor substrate is exposed, said critical pattern defining possible locations for trench capacitors and gate conductors;
(c) filling said spaces with a filler material which is selectively etchable relative to a topmost layer of said remaining stack;
(d) planarizing the filler material stopping at said topmost layer of said remaining stack;
(e) forming trench capacitors in said semiconductor substrate by etching through portions of said filler material and said substrate, wherein said etching removes a portion of said topmost layer of said remaining stack and exposes a portion of a layer of said stack that is next to the topmost layer;
(f) planarizing the remaining portion of said stack and filler material to remove the remaining portion of the topmost layer of said stack and the remaining portion of the layer that is next to the topmost layer and thereby exposing a layer of said stack that is second from the topmost layer;
(g) replacing at least a portion of either said remaining stack and/or remaining filler material with a placeholder material corresponding to locations for gate conductors; and
(h) forming said gate conductors and remaining portions of said transistors, bitlines and wordlines of said memory cell.
In one embodiment of the present invention, the trench capacitor is formed in the same stripe or block as the wordline gate conductor. This is achieved in the present invention by replacing at least a portion of the filler material with a placeholder material, See step (g) above. The first embodiment of the present invention is typically employed in fabricating 8F
2
memory cells.
In a second embodiment of the present invention, the wordline gate conductor is formed in the spaces that are between the stripes or blocks which contain the trench capacitor. This is achieved in the present invention by replacing at least a portion of the stack with a placeholder material, See step (g) above. The second embodiment of the present invention is typically employed in fabricating sub-8F
2
memory cells.
In another aspect of the present invention, memory cells are provided in which the wordline gate conductor of the cell is formed in the same stripe or block as the trench capacitor (8F
2
memory cells) or alternatively, the wordline gate conductor is formed in spaces that lay adjacent to the trench capacitors (sub-8F
2
memory cells).
REFERENCES:
patent: 4269636 (1981-05-01), Rivoli et al.
patent: 4728606 (1988-03-01), Bukhman et al.
patent: 4763180 (1988-08-01), Hwang et al.
patent: 4833516 (1989-05-01), Hwang et al.
patent: 5378911 (1995-01-01), Murukami
patent: 5389559 (1995-02-01), Hsieh et al.
patent: 5493134 (1996-02-01), Mehrotra et al.
patent: 5702987 (1997-12-01), Chen et al.
patent: 5736760 (1998-04-01), Hieda et al.
patent: 5763309 (1998-06-01), Chang
patent: 5770878 (1998-06-01), Beasom
patent: 5801417 (1998-09-01), Tsang et al.
patent: 5825704 (1998-10-01), Shau
patent: 5831301 (1998-11-01), Horak et al.
patent: 5981332 (1999-11-01), Mandenman et al.
patent: 6037210 (2000-03-01), Leas
patent: 6066526 (2000-05-01), Hakey et al.
patent: 6150210 (2000-11-01), Arnold
patent: 6204112 (2001-03-01), Chakravarti et al.
patent: 6204140 (2001-03-01), Gruening et al.
patent: 6207494 (2001-03-01), Graimann et al.
patent: 0791959-A1 (1997-08-01), None
patent: 02000200887-A (2000-07-01), None
patent: 02000252436-A (2000-11-01), None
Furukawa Toshiharu
Mandelman Jack A.
Tonti William R.
Capella, Esq. Steven
Chaudhuri Olik
International Business Machines - Corporation
Pham Hoai
Scully Scott Murphy & Presser
LandOfFree
Structure and method for planar MOSFET DRAM cell free of... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Structure and method for planar MOSFET DRAM cell free of..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Structure and method for planar MOSFET DRAM cell free of... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2516943