Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-05-04
2001-04-10
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S266000, C438S276000, C438S284000, C438S306000, C438S527000
Reexamination Certificate
active
06214668
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a structure of a non-volatile memory device and a manufacturing method and a operating method thereof. More particularly, the invention relates to a structure of a flash memory cell and a manufacturing method and operating method of the flash memory cell.
2. Description of Related Art
FIG. 1A
is a cross-sectional view showing a conventional flash memory cell structure. As shown in
FIG. 1A
, a flash memory cell
100
is formed on a substrate
10
. The flash memory cell
100
has a drain terminal
11
and a source terminal
12
in the substrate
10
lying between two adjacent field oxide layers
13
. Between the source terminal
12
and the drain terminal
11
, there is a stacked gate comprising a controlling gate
14
and a floating gate
15
. A gate voltage V
G
applied to the controlling gate
14
is used for controlling the flash memory cell
100
. The floating gate
15
is in a “floating” state without any direct connection with external circuits. Furthermore, between the substrate
10
and the source/drain terminals
11
and
12
, there is a P-well region
16
.
FIG. 1A
also shows the state of action when the flash memory cell
100
is programmed. First, a gate voltage V
G
=−9V is applied to the controlling gate
14
, a drain voltage V
D
=6V is applied to the drain terminal
11
, and a well voltage Vwell=0 is applied to the P-well
16
. No voltage is applied to the source terminal
12
and the substrate
10
, that is, the state of source terminal
12
is floating. With these applied voltages, electrons (e
−
) will eject from the floating gate
15
to the drain terminal
11
due to the edge Fowler-Nordheim effect so that the flash memory cell is programmed. However, when a voltage is applied to the drain terminal
11
, the voltage will create a depletion region
17
outside the drain terminal
11
region. Furthermore, hot holes (e
+
) will be generated leading to hot hole injection in the presence of lateral electric field. These hot holes can severely affect the normal operation of a flash memory cell.
To counteract the defects of using the above conventional technique, an improved operating mode is arranged.
FIG. 1B
is a cross-sectional view showing an improved drain structure for a conventional flash memory cell. The N
−
region
18
is used to reduce the strength of lateral electric field so as to eliminate the effect of hot hole injection, which has a better reliability.
Although the improved flash memory cell will the N
−
region
18
is able to improve the problem of hot hole injection, but with the N
−
region
18
the drain region
11
and the source region
12
become more closer, which caused the punch through occurring easily. In some cases, normal operation of neighboring flash memory cells may be affected.
FIG. 1C
is a top view showing the conventional flash memory cell structures as shown in
FIGS. 1A and 1B
. As shown in
FIG. 1C
, the active region of a conventional flash memory cell is protected and surrounded by field oxide layers
13
. Drain current flows from the drain terminal
11
to the source terminal
12
via a path labeled A. The conventional path (from source terminal to drain terminal) taken by the current is rather long, and hence has a negative effect on its efficiency. Furthermore, as the level of integration continues to increase and dimensions of each flash memory cell is reduced, a source and a drain terminal are closer together that may lead to punch through effect. Hence, in this respect, the level of integration is severely limited.
In summary, a conventional flash memory cell structure has definite limit in the level of integration. Furthermore, with a short-circuiting connection between the drain terminal and the P-well, normal operation of neighboring flash memory cells may be affected. A conventional flash memory cell structure also suffers the defects of a longer drain current path, and a shorter distance between source and drain terminals when devices are miniaturized.
In light of the foregoing, there is a need to provide an improved flash memory cell structure and its method of manufacture.
SUMMARY OF THE INVENTION
Accordingly, the present invention is to provide a channel write/erase flash memory cell structure capable of preventing any interference with neighboring source regions or any effect on the normal operation of neighboring flash memory cells due to the short-circuiting connection between a drain terminal and a P-well.
In another aspect, this invention is to provide a method of forming the aforementioned channel write/erase flash memory cell structure.
In one further aspect, this invention is to provide an operating method for operating the aforementioned channel write/erase flash memory cell structure.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a channel write/erase flash memory cell structure. The structure is formed by implanting P-type ions into a substrate to form a shallow-doped region, and then implanting N-type ions to form the drain terminal of the flash memory cell. Next, a deep-doped region that acts as a P-well is formed underneath the drain terminal by implanting P-type ions. Each P-well corresponds to a doped drain region. Consequently, even when the P-well and the doped drain region are short-circuited together, it will not affect neighboring source terminals or interfere with the normal operation of a neighboring flash memory cell. Method of manufacturing the channel write/erase flash memory cell structure and its mode of operation is also discussed.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5050125 (1991-09-01), Memedomi
patent: 5268318 (1993-12-01), Harari
patent: 5448517 (1995-09-01), Iwahshi
patent: 5554867 (1996-09-01), Ajika et al.
patent: 5589699 (1996-12-01), Araki
patent: 5696401 (1997-12-01), Mizuno et al.
patent: 5747849 (1998-05-01), Kuroda et al.
patent: 6064099 (2000-05-01), Yamada et al.
Hsu Ching-Hsiang
Yang Ching-Song
e-Memory Technology, Inc.
Elms Richard
Huang Jiawei
J C Patents
Pyonin Adam
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