Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-08-31
2001-07-10
Booth, Richard (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S592000, C438S952000
Reexamination Certificate
active
06258667
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention is in the field of integrated circuits, and is more specifically directed to the fabrication of embedded flash.
2. Description of the Prior Art
Non-volatile memory devices are important for they provide an advantage that random access memory (RAM), both dynamic and static, cannot provide. That is, non-volatile memory devices do not lose their memory even the power is turned off.
Read only memory (ROM) is the most popular variety of nonvolatile memory devices. ROMs come in a number of visions and a relatively advanced type of ROMs is the flash memory that uses a technology similar to the erasable programmable ROM.
However, the flash memory is electrically reprogrammable for a limited number of times. This makes it ideal for those applications where only a few changes in the programming of the system is for either the entire memory array or for blocks of it.
Beside, memory storage exists not only as stand-alone memory device, but also embedded in processor chips. The performance of an embedded flash can be better than other types of flash since bandwidth problems are reduced and interface circuit and package leads are eliminated. It can also have characteristic tailored to the specific application rather than being a standardized comprise between many factors such as high operating speed.
The most obvious limiting factor for an embedded flash is the cost. Another serious disadvantage of the embedded flash is relevant fabrication. Owing to the fact that in conventional fabrication both spacers and silicides of transistors of both cell (memory) region and (peripheral) logic region are formed simultaneously, conventional embedded flash has the following main disadvantages:
(1) Spacers of transistors of both peripheral region and cell region are formed by the same material. Therefore, quality of transistors of both peripheral region and cell region cannot be optimized at the same time. In other words, either performance of any transistor of a peripheral cell is degraded or reliability of any cell region is degraded.
(2) Sources/drains of transistors of cell regions are covered by silicides, therefore, junction breakdown voltage is decreased and junction leakage is increased and qualities of memory cells are degraded.
(3) The ultra-violet (UV) erasing process of the cell region is degraded by the borderless contact stop layer.
Therefore, it is indisputable that development of a new fabrication of the embedded flash to overcome these disadvantages of conventional fabrication is desired. And it is more important when the flash is an irreplaceable product of ultra large scale integration (ULSI). @
SUMMARY OF THE INVENTION
It is an object of the invention to provide a method for implementing an embedded flash that not only efficiently avoids issues of UV erasure but also efficiently avoids issue of nitride spacer stress.
It is another object of the invention to provide such a method for implementing an embedded flash where junction breakdown voltage and junction leakage of any memory cell are not degraded by saliciation.
It is a further object of the invention to provide a manufacturable fabrication of embedded flash.
In order to positively explain the invention that relates to a method of implementing an embedded flash, the embedded flash is formed on a substrate that is divided into at least a cell region and a peripheral region. Formation of the presented embodiment comprises following steps:
First, a substrate is provided that is entirely covered by a polysilicon layer. Wherein, in the peripheral region, a gate oxide layer is formed below the polysilicon layer, in the cell region, a tunneling oxide layer is formed below the polysilicon layer. Moreover, a plurality of floating gates are formed on the tunneling oxide layer, where the top of each floating gate is covered by a first dielectric layer and a sidewall of each floating gate is covered by a first thermal oxide layer.
Second, entire cell region is covered by a first photo-resist then forms a plurality of first metal oxide semiconductor transistors on the peripheral region.
Third, the first photo-resist is removed and then a self-aligned silicide process is performed to form a plurality of silicides that cover the source, drain and gate of each first metal oxide semiconductor transistor. Moreover, these silicides also cover entire cell region.
Fourth, the entire substrate is covered by an anti-reflection layer and then the entire peripheral region is covered by a second photo-resist.
Fifth, a plurality of second metal oxide semiconductor transistors are formed on the cell region. Material of a plurality of spacers of these second metal oxide semiconductor transistors can be different from material of a plurality of spacers of first metal oxide semiconductor transistors. Beside, these silicides only cover the top of each second metal oxide semiconductor transistor and the anti-reflection layer also only covers top of each second metal oxide semiconductor transistor. Additionally, a plurality of second thermal oxide layers are formed on the sidewalls of these second metal oxide semiconductor transistors before these spacers are formed.
Finally, a second dielectric layer is formed on the substrate and then a plurality of contacts are formed in said second dielectric layer. The second dielectric layer totally covers all first metal oxide semiconductor transistors and all second metal oxide semiconductor transistors.
REFERENCES:
patent: 5863820 (1999-01-01), Huang
patent: 5888869 (1999-03-01), Cho et al.
patent: 6015730 (2000-01-01), Wang et al.
patent: 6037222 (2000-03-01), Huang et al.
patent: 6069033 (2000-05-01), Verhaar et al.
patent: 6074915 (2000-06-01), Chen et al.
patent: 6096595 (2000-08-01), Huang
patent: 6096603 (2000-08-01), Chang et al.
Booth Richard
United Microelectronics Corp.
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