Semiconductor memory device having circuit for controlling...

Details Semiconductor memory device having circuit for controlling... Semiconductor memory device having circuit for controlling...

1999-09-15

2001-01-30

Elms, Richard (Department: 2824)

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

C365S194000

Reexamination Certificate

active

06181609

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, in particular, one including a circuit which internally detects the current data-output mode and controls the data output timing.
This application is based on Patent Application No. Hei 10-263569 filed in Japan, the contents of which are incorporated herein by reference.
2. Description of the Related Art
Recently, the speed of semiconductor memory devices has been increasing more and more. In a general conventional technique called the high-speed page mode, a clocking operation of a negative logic CAS (column-address strobe) signal, abbreviated as “CASB” hereinbelow, is performed so as to read data transmitted in the same word line. In the high-speed page mode, data is output to an external output pin at the falling (or decaying) timing of the CASB signal, while output data is reset and the external output pin is set to a high-impedance state (i.e., “HI-Z”) at the rising timing of the CASB signal. However, as the resetting operation of the output data (when the CASB signal rises) requires a considerable time, the high-potential state of the CASB signal must be maintained for a long time so as to increase the speed of the high-speed page mode. Therefore, it is difficult to further increase the speed.
In order to solve the above problem, EDORAM (Extended Data-Out RAM) has been developed. In the page-mode cycle of EDORAM, no data-resetting operation is performed at the rising timing of the CASB signal and data is maintained until the CASB signal of the next cycle falls. Therefore, the high-potential period of the CASB signal can be minimized so that very high speed can be achieved. Accordingly, EDORAM is currently the most common type of semiconductor memory device.
Below, the internal operations of EDORAM will be explained with reference to FIG.
4
. The address signal Ai is input into decoder
100
so as to select a memory cell in memory cell array
101
, and a target data is read out and latched by D-latch circuit
102
. The output from D-latch circuit
102
is then output via output buffer
104
. Here, in the D-latch circuit
102
, the latch operation is controlled using signal DL which is an inversion signal of signal AD output from latch signal generating circuit
1
.
Also in this arrangement, when the CASB signal falls, read data is output from the memory cell array
101
as the high-speed page mode. However, in the present case, such a falling CASB signal is delayed via a delay element and functions as signal AD. The AD is inverted into signal DL, which is used for latching the read data. Even when the potential of the CASB signal rises next time, the signal DL in synchronism with the CASB signal continues latching data. In addition, EDORAM has a specific access standard called “CASB pre-charge access time (i.e., TACP) mode” (which is not provided in a device of the high-speed page mode); thus, when the CASB signal rises, a new address must be acquired so as to start the data-read operation. Therefore, the data-latch section
102
should be positioned between the internal read-data output line and the data output buffer
104
. When the CASB signal falls next time, the above latch signal is inactivated and the latched state is finished so as to output the next read data.
Here, EDORAM has various output modes such as the tAA (i.e., address access time) mode, the above-explained tACP (i.e., CASB pre-charge access time) mode, and tCAC (i.e., CAS access time) mode.
In the tAA mode, the column address is determined in synchronism with the falling timing of the CASB signal.
In the tCAC mode, the CASB falling is made after the column address is determined and a data-read operation is internally performed and thus the data output is ready. That is, in the data-read operation in this tCAC mode, the falling of the CASB signal is kept waiting for a while.
In the tACP mode, the column address is determined when the potential of the CASB signal rises, so that the access speed at the data-reading is determined.
Hereinbelow, normal and abnormal operations of the conventional EDORAM will be explained with reference to
FIGS. 5 and 6
.
In each timing chart showing the timing of the data-read operation, the CASB signal, address signal Ai, output signal AD from the latch signal generating circuit, and signal DL which is the inversion of signal AD are included.
FIG. 6
shows waveforms in the normal operation, in a relatively low-speed cycle. In this case, tAA is shorter than tCAS (i.e., the low potential state of CASB). In such a case, it is possible to latch and hold the output data by using the signal DL. However, as the speed becomes much higher and tCAS becomes shorter than tAA as shown in
FIG. 5
, the signal DL is activated earlier than data output; thus, the output cannot be latched.
Here, both the low-potential state (i.e., the tCAS period) and high-potential state (i.e., the pre-charge period, tCP) of CASB are targets for increasing the speed. If tCAS is 20 ns or more, the operation is normally performed as shown in
FIG. 6
, but with tCAS less than 20 ns, in the tAA cycle, the tCP state appears before the read data is output, as shown in
FIG. 5
, so that data cannot be latched. If the latch timing is internally controlled (here, delayed) so as to solve the above situation, the latch signal may not be generated in a shorter tCP cycle.
SUMMARY OF THE INVENTION
In consideration of the above problems, an objective of the present invention is to provide a semiconductor memory device having a latch signal generating circuit which can latch the read data at a data-read timing corresponding to either of the minimum tCAS and the minimum tCP. As operation speeds will further increase, the data latch will become much more difficult in each cycle. The device of the present invention also targets such a future situation.
Therefore, the present invention provides a semiconductor memory device having different data-read operation cycles, comprising:
a decoder into which an address signal is input;
a matrix memory cell array consisting of a plurality of memory cells;
a D-latch circuit for latching data output from one of the memory cells which is selected by the decoder;
an output buffer for outputting the data which is output from the D-latch circuit; and
a latch signal generating circuit for generating a clock signal used in the D-latch circuit, the generated signal having a data-latch timing which is effective in each data-read operation cycle.
Typically, the kind of the semiconductor memory device is EDORAM, and the different data-read operation cycles include those appearing in an address access time, tAA, mode and a CASB pre-charge access time, tACP, mode.
Preferably, the latch signal generating circuit comprises means for detecting each necessary data-read timing by detecting the state of an external CASB signal when the address signal is changed, and determining a time suitable for latching the data according to the detected result.
The present invention also provides a similar semiconductor memory device having different data-read operation cycles, comprising: a decoder into which an address signal is input; a memory cell array consisting of a plurality of memory cells; a D-latch circuit for latching data output from one of the memory cells which is selected by the decoder; an output buffer for outputting the data which is output from the D-latch circuit; and a latch signal generating circuit which comprises:
an address transition detecting circuit, including a delay element and an exclusive OR gate, for generating a one-shot signal when the address signal is changed;
two delay elements, having different delay lengths, into which an external CASB signal is input;
an operation mode detecting circuit composed of a D-latch circuit in which the one-shot signal functions as a clock signal and into which the CASB signal is input; and
a data selector for choosing one of the outputs from the two delay elements in accordance with the potential of the output from the operation mode

Affiliated with

Also associated with

Rating

Semiconductor memory device having circuit for controlling... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory device having circuit for controlling..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device having circuit for controlling... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2511404