Bank register circuit for a multiply accumulate circuit

Details Bank register circuit for a multiply accumulate circuit Bank register circuit for a multiply accumulate circuit

1997-10-24

2001-03-13

Wiley, David A. (Department: 2781)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

Reexamination Certificate

active

06202113

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a bank register circuit for holding data to be supplied to a multiply accumulate circuit (a device for carrying out a sum-of-products operation hereafter referred to as “MAC”) of a microcomputer or a DSP (digital signal processor).
2. Description of the Prior Art
FIG. 1
shows a bank register circuit according to prior art.
The bank register circuit
100
consists of a bank register group
101
including bank registers MXA
0
to MXAn and a bank register group
102
including bank registers MAA
0
to MAAn. Data held in the bank register group
101
is supplied as input data to a sum-of-products unit
104
through an MX-bus
103
. Data held in the bank register group
102
is supplied as coefficient data to the sum-of-products unit
104
through an MA-bus
105
. The bank register groups
101
and
102
send and receive data to and from a system bus (M-bus)
106
. The sum-of-products unit
104
provides an operation result to the bank register group
101
through a Z-bus
107
, and the bank register group
101
holds the same.
FIG. 2A
shows some of the bank registers incorporated in the bank register group
101
. Each of the bank registers is composed of a write circuit
108
, a flip-flop
109
, a NOR gate
110
, a read circuit
111
, and an output circuit
112
. The write circuit
108
selects data in one of the system bus
106
and Z-bus
107
and writes the selected data into the bank register. The flip-flop
109
fetches the selected data in synchronization with a write enable signal (one of WRX
1
to WRXn) as shown in the timing chart of FIG.
3
and holds the data. The NOR gate
110
provides the NOR of the data held in the flip-flop
109
and a read enable signal (one of RDX
1
V to RDXnV). The read circuit
111
is an n-channel FET whose conductivity is controlled by the output of the NOR gate
110
and which is connected to the system bus
106
, to provide the held data to the system bus
106
at the timing shown in FIG.
3
. The output circuit
112
is a clocked inverter connected to the MX-bus
103
and provides the held data to the MX-bus
103
in response to an output enable signal (one of BX
1
to BXn). The flip-flops
109
of the bank registers are cascaded to one another through clocked inverters
113
.
FIG. 2B
shows some of the bank registers incorporated in the bank register group
102
. Each of the bank registers is composed of a flip-flop
114
, a NOR gate
115
, a read circuit
116
, and an output circuit
117
. The flip-flop
114
fetches data from the system bus
106
in synchronization with a write enable signal (one of WRA
1
to WRAn) and holds the data. The NOR gate
115
provides the NOR of the data held in the flip-flop
114
and a read enable signal (one of RDA
1
V to RDAnV). The read circuit
116
is an n-channel FET whose conductivity is controlled by the output of the NOR gate
115
and which is connected to the system bus
106
, to provide the held data to the system bus
106
. The output circuit
117
is a clocked inverter whose conductivity is controlled by an output enable signal (one of A
1
to An) and which provides the held data to the MA-bus
105
.
According to this prior art, the system bus
106
receives large capacitance from the read circuits
111
and
116
connected thereto. This capacitance increases as the number of bank registers in the bank register groups
101
and
102
, i.e., the number of read circuits
111
and
116
therein increases. Then, the read circuits
111
and
116
must have large driving capabilities. When the read circuits
111
and
116
are made of FETs as shown in
FIG. 2
, the FETs must be large. This results in increasing the size of the bank register circuit
100
, the core size of the MAC, and the chip size of the system.
Large load capacitance on the system bus
106
slows down a speed of reading data from the bank registers for the system bus
106
, to deteriorate a system operation frequency margin or a minimum operation source voltage margin.
In this way, the bank register circuit
100
of the prior art connects the read circuits
111
and
116
of the bank registers all in parallel to the system bus
106
, to greatly increase load capacitance on the system bus
106
. Each bank register having a read circuit (
111
or
116
) of large driving capability is unavoidably large to slow down a speed of reading data for the system bus
106
.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a compact bank register circuit for an MAC.
Another object of the present invention is to provide a bank register circuit for an MAC, capable of shortening a read time of data for a system bus.
In order to accomplish the objects, the present invention provides a bank register circuit for an MAC, having bank registers for holding data supplied to and received from the MAC, a dedicated write bus connected to the bank registers, for transferring data from a system bus to the bank registers, a dedicated read bus connected to the bank registers, for transferring data from the bank registers to the system bus, and a bus interface arranged between and connected to the system bus and the dedicated write and read buses, for interfacing data transfer between the system bus and the dedicated write and read buses.
According to the present invention, the timing of reading data from the bank registers for the dedicated read bus may be sooner than the timing of reading data from the bank registers for the system bus.
The bus interface of the present invention may have a write circuit made of an inverter string for writing data of the system bus into the dedicated write bus, a NAND gate for providing the NAND of a clock signal, a read control signal, and a bank register area signal that specifies a bank register, a hold circuit connected to the dedicated read bus, for temporarily holding data of the dedicated read bus, a NOR gate for providing the NOR of the output of the NAND gate and data in the dedicated read bus, and a read circuit made of an FET whose conductivity is controlled by the output of the NOR gate, for passing data from the dedicated read bus to the system bus.
Another aspect of the present invention provides a bank register circuit for an MAC, having bank registers for holding data supplied to or received from the MAC, a data transfer bus connected to the bank registers and MAC, for transferring data from a system bus to the bank registers, from bank registers to the MAC, and from the bank registers to the system bus, and a bus interface arranged between and connected to the system bus and the data transfer bus, for interfacing data transfer between the system bus and the data transfer bus.
The timing of reading data from the bank registers for the data transfer bus is sooner than the timing of reading data from the bank registers for the system bus.
The bus interface may have an inverter string including a clocked inverter whose conductivity is controlled by the product of a write control signal and a bank register area signal, for passing data from the system bus to the data transfer bus, a hold circuit connected to the data transfer bus, for temporarily holding data of the data transfer bus, a NAND gate for providing the NAND of a clock signal, a read control signal, and a bank register area signal, a NOR gate for providing the NOR of the output of the NAND gate and data from the data transfer bus, and a read circuit made of an FET whose conductivity is controlled by the output of the NOR gate, for passing data from the data transfer bus to the system bus.


REFERENCES:
patent: 4016551 (1977-04-01), Carberry
patent: 4686553 (1987-08-01), Possin et al.
patent: 4704623 (1987-11-01), Piper et al.
patent: 4837743 (1989-06-01), Chiu et al.
patent: 4912636 (1990-03-01), Magar et al.
patent: 4982247 (1991-01-01), Aoki et al.
patent: 5060145 (1991-10-01), Scheuneman et al.
patent: 5222039 (1993-06-01), Vinal
patent: 5249280 (1993-09-01), Nash et al.
patent: 5339448 (1994-08-01), Tanaka et al.
patent: 5633183 (1997-05-

Affiliated with

Also associated with

Rating

Bank register circuit for a multiply accumulate circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Bank register circuit for a multiply accumulate circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Bank register circuit for a multiply accumulate circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2509899