Semiconductor memory device and regulator

Details Semiconductor memory device and regulator Semiconductor memory device and regulator

1999-05-11

2001-01-09

Nelms, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

C365S185220, C365S185250

Reexamination Certificate

active

06172917

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a nonvolatile semiconductor memory using a flash EEPROM (electrically erasable and programmable read-only memory).
BACKGROUND OF THE INVENTION
In recent years, flash EEPROM has been widely used for various systems in industrial fields and public welfare fields because it has the advantages of being able to electrically erase and program data and being highly resistive to a shock as compared with a hard disk or the like.
To date, memory cells performing programming by CHE (channel hot electron) have been mainly employed. However, with increasing demands for a low voltage and a single power supply to the flash EEPROM, memory cell devices performing programming and erasing by FN (Fowler-Nordheim) tunneling have been developed.
FN tunneling has advantages over CHE in that the programming current is sufficiently low and a single power supply is realized by programming from a booster power supply. However, it requires several msec as a programming time per cell, and this is several tens to several hundreds times as long as the programming time of CHE.
In order to solve this problem, a page programming method is employed, in which a data latch is provided for each bit line to latch one word line of data and, simultaneously, programming and program verify are carried out.
In program verify, it is verified whether programming to the memory cells has been satisfactorily performed or not. If program verify is performed units of word lines, programming is repeated until memory cells for which programming has not been satisfactorily performed complete programming, and this causes a problem relating to reliability, such as drain disturbance.
In order to avoid this problem, there is proposed a method in which data stored in the latches connected to the memory cells for which programming has been completed are rewritten so that further programming is not performed on these memory cells.
Hereinafter, an example of program verify by the conventional flash EEPROM will be described with reference to FIG.
23
.
FIG. 23
is a diagram illustrating a column latch circuit included in the above-mentioned DINOR flash EEPROM. In
FIG. 23
, L
1
is a latch for storing data to be programmed. TG is a transfer gate which electrically separates a main bit line MBL
0
from the latch L
1
. P
1
and P
2
are transistors for precharging the bit line according to the data stored in the latch L
1
and a /PCO signal. SG
0
is a select transistor which electrically separates the main bit line MBL
0
from a sub bit line SBL
0
. Likewise, SG
1
is a select transistor which electrically separates a main bit line MBL
1
from a sub bit line SBL
1
. MEM
0
and MEM
1
are memory cells having control gates connected to a word line WL, sources connected to a source line SL, and drains connected to the sub bit lines SBL
0
and SBL
1
. The source line SL is grounded when an ASL signal becomes active. RS
1
and RS
2
are transistors for resetting the main bit lines, and the main bit lines are grounded by RSO and RSE.
Next, the operation of the column latch circuit so constructed will be described.
Although the circuit shown in
FIG. 23
has two main bit lines MBL
0
and MBL
1
, programming and program verify on the main bit line MBL
0
side will be described hereinafter.
Initially, when input data is latched by the latch L
1
, the supply voltage Vpp of the latch L
1
is maintained at Vcc level. After all the data is latched, Vpp is increased to 6V which is the programming voltage of the memory cell. At this time, the selected word line WL is maintained at −8V while the control signal SGL of the select gate SG
0
is maintained at 10V. Next, the transfer gate TG becomes active, and the latch L
1
and the main bit line MBLO are electrically connected. When the data held by the latch L
1
is “1”, 6V is applied to the main bit line MBL
0
, and when it is “0”, 0V is applied to the main bit line MBL
0
. Since −8V is applied to the control gate of the memory cell MEM
0
, when 6V is applied to the drain, an electric field occurs in the tunnel oxide film, and electrons stored in the floating gate are drawn to the drain side by an FN current. On the other hand, when the drain is at 0V, programming to the memory cell is not carried out because the electric field does not reach the strength at which a tunnel current occurs.
In program verify, Vpp is at Vcc level, and a voltage of Vcc level is applied to the main bit line MBL
0
from the precharging transistors P
1
and P
2
in accordance with the data stored in the latch L
1
.
Next, a verify voltage of 1.5V is applied to the word line WL of the memory cell, and the source line SL is grounded by the enable signal ASL. When the threshold voltage of the memory cell is lower than 1.5V, discharging of the main bit line MBL
0
is performed through the memory cell and the latch L
1
detects it. At this time, the data in the latch L
1
is rewritten and further programming is not performed. If the threshold voltage is higher than 1.5V, the initially set data is maintained as it is in the latch L
1
, and programming is performed until the data in the latch L
1
is rewritten.
In the above-described construction, however, since the latched data must be rewritten by lowering the voltage of the main bit line by the memory cell current, stable verify is not achieved.
That is, the transistor of the latch L
1
is able to supply a current larger than the sum of the values of the following currents: inter-band tunnel current which occurs between the drain and the substrate during programming, FN tunnel current, and leakage current from non-selected memory cells. However, in program verify, since the voltage of the control gate of the memory cell is a low voltage in the vicinity of the threshold voltage of the programmed memory cell, a sufficient cell current cannot be not secured, resulting in a problem that the latched data cannot be rewritten.
SUMMARY OF THE INVENTION
The present invention is made to solve the above-described problems and it is an object of the present invention to provide a nonvolatile memory device which can reliably rewrite data stored in latches when program verify is performed.
It is another object of the present invention to provide a nonvolatile memory device which can avoid, in program verify, error decision due to leakage current of non-selected memory cells by arbitrarily setting threshold voltages of memory cells and narrowing the distribution of the threshold voltages.
It is still another object of the present invention to provide a nonvolatile memory device which can reduce the programming time and the program verify time.
Other objects and advantages of the invention will become apparent from the detailed description that follows. The detailed description and specific embodiments described are provided only for illustration since various additions and modifications within the scope of the invention will be apparent to those of skill in the art from the detailed description.
According to a first aspect of the present invention, there is provided a semiconductor memory device having nonvolatile memory cells arranged in matrix, and the device comprises: bit lines connected to drains of the memory cells; latches provided for the respective bit lines or in the ratio of one latch to some bit lines; transfer gates for electrically separating the respective latches from the bit lines; bit line voltage detection circuits for detecting voltages of the respective bit lines; and latch reset circuits for inverting data stored in the respective latches in accordance with the outputs from the bit line voltage detection circuits. Therefore, the data stored in the latches can be rewritten even by a slight memory cell current, resulting in a nonvolatile memory device performing stable program verify.
According to a second aspect of the present invention, the semiconductor memory device of the first aspect further comprises: means for precharging a bit line which is selected from the bit lines connected to the drains of the memo

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