Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1998-06-12
2001-05-22
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
Reexamination Certificate
active
06237121
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of integrated circuit testing and, more particularly, to a technique for performing register-transfer-level scan selection.
2. Background of the Related Art
It is generally known in the semiconductor industry that the testing of integrated circuits comprising thousands or millions of transistors requires complex techniques and specialized test equipment. For example, in a typical processor chip, such as the processors manufactured by Intel Corporation, a variety of different devices are fabricated on a chip. Execution units (both integer and floating point), regular memory, cache memory, register files, decoders, buffers, buses, as well as other circuitry are resident on chip. Thus, the complexity of testing such devices has magnified as more transistors and functions are placed on the chip.
One common method for testing integrated circuits is the use of scan design techniques. In a typical scan technique, specialized circuits are designed into the chip and activated when a test mode is enabled. The activation of the test mode permits a variety of test inputs to be made through the specially designed test circuitry. Then, the integrated circuit is operated under normal mode for one or more clock cycles. Subsequently, the test mode is enabled again and some of the contents of registers and sequential elements internal to the integrated circuit (or portion thereof) are scanned out of the circuit, which is then monitored to determine if the correct results are noted.
A full scan selection technique will test most of the nodes in the circuit to determine the validity of the device, since all sequential elements are made controllable and observable using the scan design. However, full scan selection requires considerable chip space to include the scan design-for-test circuitry required for the scan. In lieu of full scan, partial scan selection techniques have been devised to scan only some of the sequential elements in the circuit. For example, U.S. Pat. No. 5,043,986 describes a method for partial scan testability.
When partial scan selection is utilized for testing, the manner in which circuits are to be scanned can determine the performance of the test technique and the quality of the test generated. For example, the U.S. Pat. No. 5,043,986 patent teaches the elimination of cycles (feedback paths) of desired length to select only a small fraction of the total memory elements of a circuit. Other methodologies develop on partial scan selection to identify which circuits are to be included in the scan path. See for example, “Incomplete Scan Path With An Automatic Test Generation Methodology” by Erwin Trischler, IEEE Test Conference, pp. 153-162, 1980; “On Determining Scan Flip-Flops in Partial-Scan Designs” by D. H. Lee et al., IEEE, pp. 322-325, 1990; “A New Test Generation Method for Sequential Circuits” by D. H. Lee et al., IEEE, pp. 446-449, 1991; “Integrating Scan Into Hierarchical Synthesis Methodologies” by J. Beausang et al.; International Test Conference, IEEE, pp. 751-756, 1996; “Peripheral Partitioning and Tree Decomposition for Partial Scan” by A. Balakrishnan et al., IEEE, pp. 181-186, 1997; and “H-Scan+: A Practical Low-Overhead RTL Design-for-Testability Technique for Industrial Designs” by Toshiharu Asaka et al., International Test Conference, IEEE, pp. 265-274, 1997.
Although a variety of methodologies exist for partial scan of integrated circuits for testing purposes, the prior art design techniques operate at the circuit level. That is, design criteria for the selection of the sequential circuit components which are to be modified for scanning are performed at the logic gate level. For example, the U.S. Pat. No. 5,043,986 patent provides a method of partial scan design for chip testing, in which the selection of scan memory elements eliminates cycles in the circuit while the circuit is in a test mode. By eliminating cycles of desired lengths, the set of scan memory elements may be only a small fraction of the total memory elements of a circuit. Accordingly, the scan selection looks to the scanning of certain selected circuit components at the logic gate level. The gate level circuit is one that consists of various types of logic gate level elements (such as AND, OR, NAND, etc., inverters, latches and flip-flops).
Although the partial scan selection of circuit components at the logic gate level can provide for optimized presence and usage of test circuitry on integrated circuit chips, it can become very cumbersome to implement in very dense chips, such as a processor chip. Due to a very large number of elements present in a logic gate level netlist, conventional gate level tools take a significant amount of time to select a scan configuration. Register-transfer-level (RTL), on the other hand, is a design specification which is a hierarchy above the circuit level and is utilized extensively for the design of processor chips. It would be advantageous to adapt a scan selection design technique for use at the RTL.
A disadvantage of using the previously known logic gate level partial scan selection techniques is illustrated in
FIGS. 1-3
. In
FIG. 1
, a number of gate level sequential circuit elements
10
a-c
and
11
a-c
associated with a particular logic circuit
12
(such as a combinational logic) are shown. Sequential circuit elements
10
a
-
10
c
provide the inputs to the logic circuit block
12
. The circuit elements
11
a-c
are coupled to receive as inputs a set of output from the logic block
12
. After capturing them, the elements
11
a-c
generate outputs that are fed as inputs to another logic circuit
13
. The outputs of the elements
11
a-c
will depend on the values transferred from the elements
10
a-c
and input signal(s) to the logic block
12
. The outputs of the logic circuit block
13
are then coupled back to the elements
10
a
-
10
c
to change the values (or status) of these elements. Thus, in normal operation, the input signals are processed by the logic block
12
, along with the signal values from elements
10
a
-
10
c
, to generate output signal(s) from the logic block
12
, as well as the signal changes that are captured by the sequential elements
11
a-c
. A similar sequence of events occurs with the elements
11
a-c
and logic block
13
to generate signals back to elements
10
a-c.
When current methodologies for partial scan selection are used, some of the gate level elements are selected. In the illustration, elements
11
a
,
11
c
and
10
b
are scanned, typically in a sequential fashion. This is shown by the dotted line coupling the three shaded elements. The shading indicates the elements selected for scanning, which elements (or cells)
11
a
,
11
c
and
10
b
will include test circuitry necessary to execute the scan (or test) a variety of such test circuitry are known in the art for performing the scan, including the test circuits described in the earlier-mentioned U.S. Pat. No. 5,043,986 patent. In the test mode, a scan signal (SCAN IN) is coupled to the three selected elements
11
a
,
11
c
and
10
b
and the output (SCAN OUT) of the last sequential cell is used to read the test results This is done by first loading the sequential cells
11
a
,
11
c
and
10
b
in a serial fashion like a shift register whose input is (SCAN IN). This forms the basis of the scan. The clock is pulsed through a certain number of cycles. The resulting values captured in the scan sequential elements
11
a
,
11
c
and
10
b
are then shifted out in a serial fashion and observed at the output (SCAN OUT). This is the general technique of operating scan at the logic gate level. Again a variety of techniques are known for making the selection of a portion of the flip-flops, latches and logic gates present on the chip.
A disadvantage of this approach is shown in FIG.
2
. In
FIG. 2
, the various gate level logic elements are shown formed into a register. A register format is any configuration of bits or data which are manipulated together at a high
Sengupta Sanjay
Yadavalli Sitaram
Blakely , Sokoloff, Taylor & Zafman LLP
De'cady Albert
Intel Corporation
Lin Samuel
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