Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-10-08
2001-05-15
Tsai, Jey (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S398000
Reexamination Certificate
active
06232177
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to the fabrication of a semiconductor device, and more particularly, a method for increasing a surface area of a bottom electrode for a dynamic random access memory (DRAM).
2. Description of the Related Art
Since semiconductor technique has greatly improved in recent years, a memory with a faster speed and a higher capacity has rapidly developed. In general, there are two ways to increase the capacitance of a memory. One is to use a high dielectric constant material as a dielectric layer. For example, barium strontium titanate ((Ba, Sr)TiO
3
or BST) having a dielectric constant of about 300-500 and a low thin-film leakage current widely applies to the DRAM of 4 Gbits and beyond. The other is to increase the efficient surface area of an electrode. Since platinum (Pt) has a low leakage current, a capacitor that consists of Pt and BST is widely adopted.
FIG. 1
is a schematic, cross-sectional view showing a bottom Pt electrode according to the prior art. Referring to
FIG. 1
, a semiconductor substrate
100
has a source/drain region
102
. A silicon oxide layer
104
is formed on the substrate
100
. The silicon oxide layer
104
has a polysilicon plug
106
that couples with the source/drain region
102
. A bottom Pt electrode
110
is formed on the polysilicon plug
106
. A titanium nitride barrier layer
108
is formed between the bottom Pt electrode
110
and the polysilicon plug
106
.
Normally, the formation of the resulting structure comprises first depositing a Pt layer and then etching the Pt layer to form a bottom Pt electrode. However, Pt is a difficult material to etch. Thus, it is difficult to make Pt into different shapes such as a crown shape or a scale shape in order to increase the efficient surface area of the bottom electrode.
SUMMARY OF THE INVENTION
According to above, the invention provides a method of increasing the surface area of a bottom electrode for a DRAM. A Pt electrode having a desired appearance to increase the efficient surface area of the bottom electrode can be formed through a redox reaction according to the invention; thus, the traditional Pt etching process can be omitted.
This invention that provides a method of increasing the efficient surface area of a bottom electrode for a DRAM applies to a semiconductor substrate having a conductive plug electrically coupled with a conductive region. The method comprises forming a patterned silicon layer on the substrate, performing a etching process to etch a surface of the silicon layer into a surface having protrusions in order to increase a surface area of the silicon layer, performing a redox reaction to transform the silicon layer with the surface having protrusions into a metal layer by a solution while maintaining the original shape of the silicon layer, and performing an annealing process to concentrate the metal layer in order to reduce leakage current.
The invention provides a method of increasing the efficient surface area of a bottom electrode for a DRAM and a method of forming a capacitor that consists of the bottom electrode. The methods comprise the following steps. A semiconductor substrate that has a conductive plug coupled with a conductive region such as a source/drain region is provided. A barrier layer and a silicon layer are formed on the semiconductor substrate, and the barrier layer and the silicon layer are patterned to a bottom pattern aligned to the conductive plug. An etching process is performed to etch a surface of the silicon layer into a surface having protrusions in order to increase a surface area of the silicon layer. A bottom electrode with a surface having protrusions is formed by performing a redox reaction by use of a solution to transform the silicon layer with the surface having protrusions into a metal layer such as a platinum (Pt) layer or a palladium (Pd) layer while maintaining the original shape of the silicon layer. An annealing process is performed to concentrate the metal layer in order to reduce leakage current, a dielectric layer, such as a barium strontium titanate (BST) layer, having a high dielectric constant, a conductive layer such as a Pt or Pd layer is formed as a top electrode on the dielectric layer.
The invention provides a method to efficiently increase the surface area of a bottom electrode for a DRAM. The invention can provide an electrode with different shapes in order to increase the surface of the bottom electrode of a capacitor by nontraditional etching process. Thus, the invention preserves the advantage of the Pt electrode in a capacitor in increasing the capacitance of the capacitor and can apply to the DRAM process.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5427974 (1995-06-01), Lur et al.
patent: 5563090 (1996-10-01), Lee et al.
Chang Ting-Chang
Liu Po-Tsun
Thomas Kayden Horstemeyer & Risley
Tsai Jey
United Microelectronics Corp.
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