Electrolysis: processes – compositions used therein – and methods – Electrolytic erosion of a workpiece for shape or surface... – Electrolyte composition or defined electrolyte
Reexamination Certificate
1998-09-29
2001-03-20
Gorgos, Kathryn (Department: 1741)
Electrolysis: processes, compositions used therein, and methods
Electrolytic erosion of a workpiece for shape or surface...
Electrolyte composition or defined electrolyte
C205S684000
Reexamination Certificate
active
06203690
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is directed to the process of reworking pin grid array chip carriers, and more particularly, to the process of reworking pin grid array chip carriers using an electrolytic etch process.
2. Description of the Related Art
Ceramic, glass and glass-ceramic substrates have been widely used in the computer industry as chip carriers, wherein semiconductor integrated circuit chips are attached to the substrate. The chip carriers may be single layer or multilayer and may be also single chip or multichip. A particular kind of chip carrier is called a pin grid array (hereafter PGA) chip carrier wherein input/output (hereafter I/O) pins are used to connect the PGA chip carrier to the next level of packaging, usually a card.
In the manufacturing of a PGA, the I/O pins are brazed to I/O pads on a surface of the PGA chip carrier. Thereafter, the pins are nickel and gold electroplated. During the plating operation, all pins must contact a common electrode, for example the electrically conductive foil disclosed in Canaperi et al. U.S. Pat. No. 5,516,416, the disclosure of which is incorporated by reference herein, to pass current to them and carry on the plating process. A poor contact, or a complete lack of contact, with the electrode results in unplated I/O pins. Unplated I/O pins are unacceptable and must be reworked.
Further, if the gold plating was too thick or too thin on the I/O pins, the I/O pins would also have to be reworked.
It is not feasible to plate pins on a one-by-one basis so it is necessary to rework all the I/O pins.
The following references illustrate the state of the pertinent art.
Layher et al. U.S. Pat. No. 4,914,813, the disclosure of which is incorporated by reference herein, discloses the rebuilding of PGA chip carriers which includes removing the I/O pins and other metallurgy, replating the I/O pads, brazing new I/O pins to the I/O pads and replating the I/O pins with nickel and gold.
Yu et al. U.S. Pat. No. 5,722,579, the disclosure of which is incorporated by reference herein, discloses a method of reworking a PGA chip carrier which includes shearing off the I/O pins, polishing the surface of the PGA chip carrier, laying down new I/O pads and attaching new I/O pins.
A current rework process consists of shearing the I/O pins off, etching of any leftover braze, replating of top and bottom surface metallurgy, pin braze with new pins and plating of the new pins.
Such a process is time consuming and expensive. It would be desirable to have a rework process which is less time consuming and less expensive.
Accordingly, it is a purpose of the present invention to have a process for reworking PGA chip carriers wherein the entire PGA chip carrier does not need to be reworked in order to rework just the I/O pins.
It is another purpose of the present invention to have a process for reworking PGA chip carriers which is less time consuming and less expensive.
BRIEF SUMMARY OF THE INVENTION
The present invention relates to a method of reworking PGA chip carriers having at least one unplated I/O pin, the method comprising the steps of:
a. obtaining a PGA chip carrier having at least I/O pin that is plated with gold over nickel and at least one I/O pin that is unplated but contains a corrosion product where the I/O pin should be plated;
b. electrolytically etching the I/O pins with an aqueous etching solution comprising:
a metal-providing compound selected from the group consisting of a silver salt, copper salt, copper cyanide, silver cyanide, gold cyanide or mixtures thereof, at a concentration in the range from about 1 to about 6 g/l as metal;
potassium or sodium carbonate at a concentration in the range from about 10 to about 100 g/l; and
potassium or sodium cyanide at a concentration in the range from about 29 to about 35 g/l,
wherein the etching solution temperature is in the range from about 20 to about 30° C., the etching solution pH is in the range from about 11.5 to about 13, and the current density is in the range from about 7.5 to about 9.5 mA/cm
2
, and wherein the plated I/O pin is stripped of gold and the unplated pin is stripped of corrosion product.
REFERENCES:
patent: 4914813 (1990-04-01), Layher et al.
patent: 5516416 (1996-05-01), Canaperi et al.
patent: 5722579 (1998-03-01), Yu et al.
patent: 5896869 (1999-04-01), Maniscalco et al.
Findeis Paul F.
Gauci John P.
Semkow Krystyna W.
Weisman Renee L.
Blecker Ira D.
Gorgos Kathryn
International Business Machines - Corporation
Parsons Thomas H
LandOfFree
Process of reworking pin grid array chip carriers does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Process of reworking pin grid array chip carriers, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Process of reworking pin grid array chip carriers will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2503944