Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-09-03
2001-07-10
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S241000, C438S253000, C438S622000, C438S666000, C438S791000
Reexamination Certificate
active
06258649
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit device and to a technique for the manufacture, thereof and, more particularly, the invention relates to a technique which is effective for application to a semiconductor integrated circuit device having a DRAM (Dynamic Random Access Memory).
Memory cells of a DRAM are respectively placed at points where a plurality of word lines and a plurality of bit lines, disposed over a principal or main surface of a semiconductor substrate intersect in matrix form. The memory cell comprises one memory cell selection MISFET (Metal Insulator Semiconductor Field Effect Transistor) and one information capacitive element (capacitor) electrically connected in series with the memory cell selection MISFET.
The memory cell selection MISFET is formed in an active region whose periphery is surrounded by a device separation region The memory cell selection MISFET is composed principally of a gate oxide film, a gate electrode formed integrally with each word line, and a pair of semiconductor regions which form a source and a drain. Each bit line is placed above the memory cell selection MISFET and is electrically connected to one of the source and drain shared by two memory cell selection MISFETs disposed adjacent to each other in its extending direction. Similarly, the information storage capacitive element is disposed above the memory cell selection MISFET and is electrically connected to the other of the source and drain.
Japanese Patent Application Laid-Open No. Hei 7-7084 discloses a DRAM of a capacitor over bitline (COB) structure wherein information storage capacitive elements are placed over the bit lines. According to the DRAM described in the publication, a lower electrode (storage electrode) of each information storage capacitive element disposed above the bit line is processed into cylindrical form to make up for a reduction in the amount of an electrical charge stored in each information storage capacitive element with macro-fabrication of each memory cell, whereby the surface area thereof is increased, and a capacitive insulating film and an upper electrode (plate electrode) are formed over the lower electrode.
According to the DRAM described in the publication as well, a frame-shaped groove (channel), which surrounds a memory array, is defined in the boundary between the memory array and a peripheral circuit region, and a thick insulating film is deposited over the peripheral circuit region outside the channel, whereby a step-like offset between the memory array and the peripheral circuit is settled and the flattening of the peripheral circuit region is implemented together. The groove is defined simultaneously in a process step for processing the lower electrode of each information storage capacitive element into cylindrical form. An inner wall of the groove is composed of the same material (polycrystal silicon film) as the lower electrode.
SUMMARY OF THE INVENTION
According to the DRAM of the prior art, since the wall surface of the lower electrode which is processed into cylindrical form, is utilized as an effective region for ensuring the amount of stored electrical charges, the height of the lower electrode and the depth of the groove (channel) increase as each memory cell is miniaturized. With such increase in size, the insulating film formed in the peripheral circuit region lying outside the groove (channel) also further increases in thickness. As a result, a through hole for connecting an upper-layer wire or interconnection formed over the thick insulating film in the peripheral circuit region and a lower-layer interconnection formed below the insulating film also further increases in aspect ratio (depth/diameter of the through hole).
However, when the aspect ratio of the through hole defined in the thick insulating film in the peripheral circuit region increases, a through hole defined in an insulating film between a feeding interconnection for supplying predetermined power to the upper electrode of each information storage capacitive element and the upper electrode and a through hole for connecting an upper-layer interconnection formed over a thick insulating film in a peripheral circuit region and a lower-layer interconnection formed below the insulating film are greatly different in aspect ratio from each other. Therefore, when one attempts to simultaneously form the two through holes in the same process step, the through hole having a small aspect ratio, which is formed over the upper electrode of the information storage capacitive element, is over-etched when an etching condition for the insulating film is matched to the through hole having the large aspect ratio in the peripheral circuit region, thereby penetrating the upper electrode. Therefore, a lower portion of the through hole might reach the lower-layer interconnection at the worst. On the other hand, when the etching condition for the insulating film is matched to the through hole having a low aspect ratio, which is formed above the upper electrode, the bottom of the through hole having the large aspect ratio, which is formed in the peripheral circuit region, does not reach the lower-layer interconnection.
In the DRAM of the prior art as well, metal interconnections corresponding to two layers are formed in a layer above each information storage capacitive element. Since these metal interconnections provided in the layer above the information storage capacitive element are formed with a thickness which is greater than an interconnection formed in a layer below the information storage capacitive element, an insulating film deposited by the normal CVD method lacks in gap-filling characteristic in an interconnection densified region and so difficulties are encounted in embedding it into spaces defined between the interconnections.
As countermeasures against this problem, one may consider that an insulating film covering the metal interconnections is deposited by a high-density plasma CVD method having an excellent gap-filling characteristic. However, the insulating film deposited by the high-density plasma CVD method has a feature that it is apt to be charged up by an electrical charge in a plasma. Therefore, when the insulating film is deposited over a feeding metal interconnection for supplying power to the upper electrode of each information storage capacitive element by the high-density plasma CVD method, electrical charges borne by charged particles in a plasma are transferred to the upper electrode through the feeding metal interconnection, whereby the information storage capacitive element might cause dielectric breakdown.
An object of the present invention is to provide a technique capable of improving the accuracy of processing of a through hole defined in an insulating film between a feeding interconnection for supplying power to an upper electrode of each capacitive element and the upper electrode to thereby enhance the connection reliability of the feeding interconnection.
Another object of the present invention is to provide a technique capable of preventing dielectric breakdown of a capacitive insulating film, which is caused by charge-up of a capacitive element upon growing an insulating film deposited over an interconnection connected to an upper electrode of the capacitive electrode.
The above, and other objects and novel features of the present invention will become more apparent from the description of the present specification and the accompanying drawings.
A summary of typical aspects and features of the invention disclosed in the present application will be briefly explained as follows:
(1) A method of manufacturing a semiconductor integrated circuit device according to the present invention includes the following steps:
(a) a step of forming memory cell selection MISFETs in a memory array region on a main surface of a semiconductor substrate and forming MISFETs for a peripheral circuit in a peripheral circuit region;
(b) a step for forming a first interconnection over the MISFET and thereafter formin
Asano Isamu
Fukuda Takuya
Hirasawa Masayoshi
Kawakita Keizo
Nakamura Yoshitaka
Antonelli Terry Stout & Kraus LLP
Anya Igwe U.
Hitachi Ltd
Smith Matthew
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