Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-10-13
2001-03-13
Booth, Richard (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S981000
Reexamination Certificate
active
06200857
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a method of manufacturing a semiconductor device having accurately dimensioned submicron features. The present invention has particular applicability in manufacturing semiconductor devices with a design rule of about 0.15 micron and under with accurately dimensioned gate electrode structures in the peripheral circuitry region.
BACKGROUND ART
The escalating requirements for high density and performance associated with ultra-large scale integration require increasingly denser arrays with reduced feature sizes. Implementation becomes problematic in manufacturing semiconductor devices having a design rule of about 0.15 micron and under, e.g., about 0.12 micron and under.
Semiconductor devices typically comprise a substrate and elements such as transistors and/or memory cells thereon. Various interconnection layers are formed on the semiconductor substrate to electrically connect these elements to each other and to external circuits. Conventional manufacturing techniques typically comprise forming memory cells in a core memory cell region and forming peripheral circuitry. Processing to form features peculiar to the core memory cell region does not usually correspond or is not necessarily optimal to processing for the peripheral circuitry region. For example, conventional methodology requires the use of at least three separate photoresist masks in the core memory cell region which are removed from the ARC overlying the gate electrode layer in the peripheral circuitry region prior to patterning the gate electrode structure in the peripheral circuitry region. Such conventional methodology requires the formation and removal of different photoresist masks for etching the stacked gate electrode structure, ion implanting impurities to form shallow source/drain extensions and ion implanting impurities to form moderate or heavily doped source/drain implants. These photoresist masks are conventionally removed from the peripheral circuitry region prior to patterning the gate electrode structure of the peripheral circuitry region. However, each time the photoresist is stripped from the ARC, some of the ARC is lost, thereby altering its functional capabilities with respect to avoiding deleterious reflections during photoresist patterning. Consequently, a loss of critical dimension is encountered upon subsequent patterning of the underlying gate electrode structure.
As miniaturization proceeds apace, the loss of dimensional accuracy, including in the peripheral circuitry region, becomes acutely problematic. Accordingly, a need exists for methodology enabling accurate patterning of a gate electrode structure in the peripheral circuitry region, notwithstanding the use of a plurality of masks in the core memory cell region which require stripping.
SUMMARY OF THE INVENTION
An advantage of the present invention is a method of manufacturing a semiconductor device having an accurately dimensioned gate electrode structure in the peripheral circuitry region.
Additional advantages and features of the present invention will be set forth in the description which follows and, in part, will become apparent to those having ordinary skill in the art upon examination of the following and may be learned from the practice of the present invention. The advantages of the present invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other advantages are achieved in part by a method of manufacturing a semiconductor device comprising a core memory cell region and a peripheral circuitry region, the method comprising the following steps: (a) forming a first gate electrode stack in the memory cell region, the first gate electrode stack comprising, sequentially: a tunnel dielectric layer; a charge storage electrode layer, e.g., a floating gate electrode layer; a dielectric layer; a control gate electrode layer, and an anti-reflective coating (ARC); (b) forming a second gate electrode stack in the peripheral circuitry region, the second gate electrode stack comprising, sequentially: a dielectric layer; a gate electrode layer; and an ARC; (c) depositing a first layer of photoresist material over the core memory cell and peripheral circuitry regions; (d) forming a first photoresist mask on the second gate electrode stack; (e) etching the second gate electrode stack, while the first gate electrode stack is masked by the first layer of photoresist material, to form a gate electrode structure comprising, sequentially: a gate dielectric; a gate electrode; and an ARC; (f) removing the first photoresist mask from the peripheral circuitry region and the first layer of photoresist material from the memory cell region; (g) forming a second photoresist layer over the core memory cell and peripheral circuitry regions; (h) forming a second photoresist mask on the first gate electrode stack; and (i) etching the first gate electrode stack to form at least one stacked gate electrode structure comprising, sequentially: a tunnel dielectric; a charge storage electrode; an intergate dielectric; a control gate electrode; and an ARC.
Embodiments of the present invention include the further manipulative steps of: removing the second photoresist mask from the memory cell region and second layer of photoresist material from the peripheral circuitry region; depositing a third layer of photoresist material over the core memory cell and peripheral circuitry regions; forming a third photoresist mask over the core memory cell region; ion implanting impurities to form shallow source/drain extension implants associated with each stacked gate electrode structure; removing the third photoresist mask from the core memory cell region and third layer photoresist material from the peripheral circuitry region; forming a fourth photoresist mask over the core memory cell region and ion implanting impurities to form moderately or heavily doped source/drain implants. Subsequent processing includes annealing to activate the ion implanted regions.
Additional advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description, simply by way of illustration of the best mode contemplated for carrying out the present invention. As will be realized, the present invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the present invention. Accordingly, the drawings and descriptions should be regarded as a illustrative in nature, and not as restrictive.
REFERENCES:
patent: 6004843 (1999-12-01), Huang
Hsiao Tommy C.
Ramsbey Mark T.
Sun Yu
Advanced Micro Devices , Inc.
Booth Richard
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