Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-05-28
2001-01-23
Booth, Richard (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S264000, C438S279000
Reexamination Certificate
active
06177315
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to high-density electrically-erasable, programmable, read-only-memory (EEPROM) devices and, in particular, to a method of fabricating a high-density EEPROM array.
2. Discussion of the Related Art
A floating-gate tunneling-oxide (FLOTOX) electrically-erasable programmable read-only-memory (EEPROM) cell is an information storage device that utilizes the non-volatile storage of an electric charge as the information storage mechanism. FLOTOX EEPROM cells differ from EPROM and flash non-volatile memory cells in that FLOTOX EEPROM cells are both programmed and erased by means of Fowler-Nordheim tunneling.
FIG. 1
shows a cross-sectional diagram that illustrates a conventional FLOTOX EEPROM cell
100
. As shown in
FIG. 1
, EEPROM cell
100
includes a memory transistor
102
which holds the electric charge, and an access transistor
104
which controls access to memory transistor
102
.
Memory transistor
102
includes buried N+(BN+) source and drain regions
114
and
116
, respectively, which are formed in a lightly-doped p-type substrate
112
, and BN+ oxide regions
118
and
120
which are grown over BN+ source and drain regions
114
and
116
, respectively. BN+ oxide region
120
, in turn, includes a tunnel window
122
that exposes a portion of drain region
116
.
As further shown in
FIG. 1
, memory transistor
102
also includes a thin layer of tunnel oxide
124
that is formed over drain region
116
in tunnel window
122
, and a thicker layer of gate oxide
126
that is formed over substrate
112
between BN+ source and drain regions
114
and
116
.
In addition, memory transistor
102
further includes a floating gate
130
which is formed over BN+ oxide regions
118
and
120
, tunnel oxide layer
124
, and gate oxide layer
126
, and a control gate
134
which is formed over floating gate
130
and isolated therefrom by a layer of interpoly dielectric
132
.
Access transistor
104
, in turn, includes a drain region
136
which is formed in substrate
112
, a BN+oxide region
138
which is grown over BN+ drain region
136
, and a channel region
140
which is defined between drain region
136
and drain region
116
(which acts as the source for access transistor
104
). Further, transistor
104
also includes a layer of gate oxide
142
which is formed on substrate
112
over channel region
140
, and an access gate
144
which is formed on gate oxide layer
142
over channel region
140
.
In operation, cell
100
is programmed by applying a program voltage, such as +12V, to control gate
134
and an access voltage, such as +5V, to access gate
144
while grounding drain region
136
and floating source region
114
. Under these bias conditions, electrons from drain region
116
tunnel through tunnel oxide layer
124
by way of the well-known Fowler-Nordheim tunneling mechanism, and begin accumulating on floating gate
130
where the increased negative charge raises the threshold voltage of the cell.
Cell
100
is erased by applying the access voltage to access gate
144
and an erase voltage, such as +12V, to drain region
136
while grounding control gate
134
and floating source region
114
. Under these bias conditions, electrons from floating gate
130
tunnel back through tunnel oxide layer
124
to drain region
116
where the reduced negative charge on floating gate
130
lowers the threshold voltage of the cell. (The thickness of gate oxide layer
126
and the magnitudes of the program and erase voltages are selected so that Fowler-Nordheim tunneling does not occur through gate oxide layer
126
.)
Once programmed or erased, cell
100
is read by applying a first read voltage, such as +1.5V, to control gate
134
, the access voltage to access gate
144
, and a second read voltage, such as +3V, to drain region
136
while grounding source region
114
. When cell
100
is erased, a large current flows from drain region
136
to drain region
116
to source region
114
due to the lower threshold voltage of an erased cell, while a much smaller current or no current at all flows from drain region
136
to drain region
116
to source region
114
when cell
100
is programmed due to the higher threshold voltage of a programmed cell.
U.S. Pat. No. 5,856,222 to Bergemont et al. disclosed a FLOTOX EEPROM cell and a method of fabricating the cell that utilized a floating-gate access transistor.
FIG. 2
shows a cross-sectional diagram that illustrates an EPROM cell
200
as disclosed by Bergemont. Cell
200
is similar to cell
100
and, as a result, utilizes the same reference numerals to designate the structures which are common to both cells.
As shown in
FIG. 2
, one way that cell
200
differs from cell
100
is that cell
200
utilizes a double-poly access transistor
204
. Specifically, access transistor
204
includes a floating gate
210
which is formed over channel region
140
, a layer of interpoly dielectric
212
which is formed on floating gate
210
, and a control gate
214
which is formed on dielectric layer
212
.
FIGS.
3
A-
3
E show a series of cross-sectional views that illustrate a process flow for fabricating EEPROM cell
200
. As shown in
FIG. 3A
, the process begins by forming a layer of oxide
312
approximately 500 Å thick on a conventionally formed p-type substrate material
310
, such as a well or a substrate.
Following this, a mask
314
is formed and patterned on oxide layer
312
to expose a region on the surface of oxide layer
312
. The exposed region is then implanted with an n-type dopant to form a buried n+ region
316
in material
310
. Following the implant, mask
314
is removed.
As shown in
FIG. 3B
, after mask
314
has been removed, the exposed region of oxide layer
312
is etched away to form an exposed region on the surface of material
310
. Next, a layer of tunnel oxide
320
approximately 70 Å thick is formed on the exposed region of material
310
.
As shown in
FIG. 3C
, once tunnel oxide layer
320
has been formed, a layer of first polysilicon (poly-1)
322
is formed on oxide layer
312
and tunnel oxide layer
320
. The layer of poly-1
322
is then conventionally doped. A layer of interpoly dielectric material
324
is formed on poly-1 layer
322
. Dielectric layer
324
is typically implemented with oxide
itride/oxide (ONO).
Following this, a layer of second polysilicon (poly-2)
326
is deposited on ONO layer
324
. After poly-2 layer
326
has been formed, a mask
330
is formed and patterned on poly-2 layer
326
. The unmasked regions of poly-2 layer
326
, and the underlying layers of ONO and poly-1 are then etched.
The etch forms a memory-transistor stacked-gate structure
332
, an access-transistor stacked-gate structure
334
, a pair of exposed regions
336
on the surface of oxide layer
312
, and an exposed region
338
on the surface of tunnel oxide layer
320
.
Poly-1 layers
322
in structures
332
and
334
form floating gates
130
and
210
, respectively, while poly-2 layers
326
in structures
332
and
334
form control gates
134
and
214
, respectively, which are self-aligned to the floating gates
130
and
210
. Following the etch, mask
330
is removed.
As shown in
FIG. 3D
, once mask
330
has been removed, the exposed regions
336
and
338
are then implanted with an n-type dopant to form a lightly-doped source region
340
A and a lightly-doped drain region
342
A in material
310
. (The implant also increases the dopant concentration of region
316
.)
Next, a layer of oxide (not shown) is then formed on oxide layer
312
, tunnel oxide layer
320
, and structures
332
and
334
, and then anisotropically etched to form spacers
344
adjacent to the sidewalls of structures
332
and
334
.
As shown in
FIG. 3E
, spacers
344
reduce the size of the exposed regions formed over the source and drain regions
340
A and
342
A. The reduced-size exposed regions are then implanted to form heavily-doped source and drai
Bergemont Albert
Kalnitsky Alexander
Booth Richard
Limbach & Limbach L.L.P.
National Semiconductor Corporation
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