Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-01-19
2001-05-29
Quach, T. N. (Department: 2814)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S239000, C438S624000, C438S629000, C438S639000, C438S738000
Reexamination Certificate
active
06238961
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a semiconductor device and a technique for manufacturing the same, and particularly to a technique effective for application to a dynamic Random Access Memory (DRAM), which requires a storage holding operation fit for high integration.
BACKGROUND OF THE INVENTION
A trench type and a stacked type have generally been known as a basic structure of a DRAM. The trench type is one wherein each of capacitative elements (hereinafter called simply “capacitors”) for information storage is formed inside a trench defined in a substrate. The stacked type is one wherein each of capacitors is formed over its corresponding transfer transistor (hereinafter called selection MISFET (Metal Insulator Semiconductor Field Effect Transistor)) on the surface of a substrate. The stacked type is further classified into a CUB (Capacitor Under Bit-line) type wherein each capacitor is placed below its corresponding bit line and a COB (Capacitor Over Bit-line) type wherein each capacitor is located over the bit line. 64M-bit and later products which have gone into mass production, are of stacked types excellent in characteristic of a reduction in each cell area. The COB type is becoming mainstream.
A structure of a DRAM having each COB type memory cell is illustrated by way of example as follows. Namely, The memory cells of the DRAM having the COB type memory cells are placed at points where a plurality of word lines and a plurality of bit lines placed on a main surface of a semiconductor substrate in matrix form intersect respectively. Each memory cell comprises one selection MISFET and one capacitor electrically connected to the selection MISFET. The selection MISFET is formed in an active region whose periphery is surrounded by device isolation regions, and is comprised principally of a gate oxide film, a gate electrode formed integrally with each word line, and a pair of semiconductor regions each constituting a source and drain. Each of the bit lines is placed over its corresponding selection MISFET and electrically connected to one of the source and drain shared between two selection MISFETs adjacent in its extending direction. Similarly, each capacitor is placed over its corresponding selection MISFET and electrically connected to the other of the source and drain. In order to supplement a reduction in the amount (Cs) of an electrical charge stored in each capacitor due to scaling down of each memory cell, a lower electrode (storage electrode) of the capacitor placed over the bit line is processed in cylindrical form to increase a surface area thereof, and a capacitive insulating film and an upper electrode (plate electrode) are formed thereover.
In such a structure of COB type memory cell, the bit lines and the source and drain regions of the selection MISFET are electrically connected to one another by plugs each composed of a polycrystalline silicon film or the like. Since plugs for capacitor connection are also formed simultaneously with plugs for bit line connection in general, at least an insulating film corresponding to one layer is formed between the plug and bit line to isolate the bit line and the plug for capacitor connection from each other. Thus, the bit lines and the plugs are connected to one another through bit line connecting holes respectively. There is a demand for a reduction in the capacitance of each bit line in terms of an improvement in the operating speed of a DRAM and an improvement in the sensitivity for the detection of each stored charge. There is further a demand for scaling down or miniaturization of members such as the bit lines even in terms of the implementation of scaling down. In order to meet these demands, a technique is known wherein the bit lines are formed by a damascene method and side wall spacers each composed of a silicon nitride film are formed over inner side walls as described in the international publication WO98/28795, for example. Owing to such a technique, the bit lines are made thin and the distance between the bit lines is made long to reduce the capacitance between the bit lines, whereby the speeding up of the DRAM and the sensitivity for the detection of each stored capacitance are improved.
SUMMARY OF THE INVENTION
When bit lines are connected to their corresponding connecting plugs through bit line connecting holes, it is necessary to form patterns for the bit lines and patterns for the bit line connecting holes by different masks. Word lines each of which also serves as a gate electrode of each MISFET, are normally formed after isolation regions are formed over a main surface of a semiconductor substrate. Thereafter, connecting plugs are formed. Further, when the bit lines are formed by the damascene method, the bit line connecting holes are defined after the formation of trenches for the bit line patterns, and the bit lines to be connected to their corresponding connecting plugs are formed by a so-called dual damascene method. Here, lithography for the formation of the connecting plugs is carried out on the basis of a word line pattern corresponding to the gate electrode of each MISFET. However, since the connecting plug for the bit line connection and the connecting plug for the capacitor connection are generally formed in common, a pattern for a bit line and a pattern for a bit line connecting hole, which are to be next formed, are not subjected to photolithography on the basis of the connecting plug and subjected to photolithography on the basis of the word line pattern in a manner similar to the connecting plug. Namely, the pattern for the bit line and the pattern for the bit line connecting hole are brought to three interlayer alignment, so that pattern misalignment is liable to occur. In particular, a shift in alignment or misalignment between each bit line and its corresponding bit line connecting hole does not cause a problem so far in a word-line vertical direction because each bit line is formed so as to extend in the word-line vertical direction. However, the magnitude of the misalignment influences a connecting area as it is in the direction parallel to the word line, thus resulting in a large possibility that a problem will occur.
In the prior art, the side wall spacers each composed of the silicon nitride film are formed over the inner side walls of the trench defined in each bit line pattern as the method for making each bit line thin. However, this leads to the factors that the permittivity of the silicon nitride film is made large and the capacitance between the bit lines is increased. The increase in the capacitance between the bit lines is undesired because the sensitivity for the detection of each storage capacitance is lowered and the operating speed of the DRAM is reduced.
An object of the present invention is to provide a technique capable of implementing electrical connections between a bit line and a connecting plug on a self-alignment basis in a word line direction in each memory cell of a scaled-down DRAM, and a technique capable of implementing electrical connections between a bit line and a connecting plug with ease and a high degree of reliability.
Another object of the present invention is to simplify a process for forming portions where bit lines and connecting plugs are connected to one another.
A further object of the present invention is to reduce the capacitance between adjacent bit lines.
The above, and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
Summaries of typical ones of the inventions disclosed in the present application will be described in brief as follows:
(1) A process for manufacturing a semiconductor device, according to the present invention comprises (a) a step for forming isolation regions on a main surface of a semiconductor substrate and arranging a plurality of active regions each having a long side in a first direction, (b) a step for forming first interconnections each extending in a second direction orthogonal to th
Asano Isamu
Tsuchiya Osamu
Antonelli Terry Stout & Kraus LLP
Hitachi , Ltd.
Quach T. N.
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