Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-12-06
2001-04-17
Chaudhuri, Olik (Department: 2814)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S290000, C438S294000, C438S308000
Reexamination Certificate
active
06218249
ABSTRACT:
BACKGROUND AND SUMMARY OF THE INVENTION
This invention relates generally to semiconductor technology and more particularly to the formation of silicided electrodes in active semiconductor devices, such as MOS transistors.
An important subject of ongoing research in the semiconductor industry is the reduction in the dimensions of devices used in integrated circuits. Planar transistors such as metal oxide semiconductor (MOS) transistors are particularly suited to use in high density integrated circuits. As the size of MOS transistors and other active devices decreases, the dimensions of the source/drain/gate electrodes, and the channel region of each device, decrease correspondingly.
The design of ever smaller planar transistors with short channel lengths makes it necessary to provide very shallow source/drain junction regions. Shallow junctions are necessary to avoid lateral diffusion of implantation dopants into the channel such diffusion being undesirable because it contributes to leakage currents and poor breakdown performance. Shallow source/drain junction regions, for example, less than 1000 angstroms (Å) thick, and preferably less than 500 Å thick, are necessary for acceptable performance in short channel devices.
When shallow junction electrodes are used in transistors, it becomes more difficult to provide reliable, low resistance connections to the source/drain regions of the device. Metal-silicide contacts are a typical means of effecting such connections to source/drain/gate electrodes. In such contacts, conductive metal is deposited on the silicon electrodes and annealed to form a metal-silicon compound on the surface of the electrodes. The compound, called silicide, is electrically and physically bonded to the electrode, and has a substantially lower sheet resistance than the silicon on which it is formed. An important advantage of silicide contacts in small devices is that silicide is only formed where the deposited metal is in contact with silicon. By means of a selective etch, the metal is readily removed from the non-silicided areas. Thus, the silicide regions are automatically aligned on the electrode surfaces only. This self-aligned silicide process is generally referred to as the “salicide” process.
One difficulty presented by the salicide process on shallow junction source and drain regions is that it consumes a portion of the surface silicon. The metal-silicide is formed from a chemical reaction which occurs during an annealing step, when the deposited metal reacts with the underlying silicon. Electrodes with very thin junction depths have less silicon to sacrifice to the formation of silicide, and can only permit a very thin layer of silicide to be formed. But thin silicide films are known to be thermally unstable and have an undesirably high sheet resistance.
One prior art technique for increasing the thickness of the silicide contacts is to deposit additional silicon on the surface of the doped source and drain regions. The additional silicon in the raised source and drain electrodes can then be used in the reaction with deposited metal to form thicker silicide layers. This solution has disadvantages because the deposition of additional silicon produces additional diffusion of dopants, and addition process steps and costs to IC production.
It is a well observed fact that inconsistent junction leakage currents often result from the salicidation of source/drain electrodes. It is believed that the random leakage phenomena is the result of silicide edges. The formation of “excess” silicide, into the source/drain areas around the edges of the source/drain electrodes, and in close proximity to the metallurgical edges of the junction areas underlying the source/drain electrodes, leads to the leakage current problem. These incursions, perturbations, or areas of increased thickness of silicide cause large electric field variances, and may even permit electrical conductivity extending through the junctions. While the amount of silicide formed on the main body of the source/drain electrodes is controlled by the thickness of the deposited silicidation metal, additional supplies of the metal are available around the edges of the source/drain electrodes where the metal is deposited on non-reacting surfaces, such as oxides.
A co-pending patent application entitled NITRIDE OVERHANG STRUCTURE FOR THE SILICIDATION OF TRANSISTOR ELECTRODES WITH SHALLOW JUNCTIONS, invented by Maa et al., filed on Feb. 13, 1998, and assigned to the same assignees as the instant patent application, presents a solution to the problem of silicided edges. In the above-mentioned application, a temporary nitride sidewall structure is used to prevent the deposition of silicidation metal on the edge of the source/drain electrodes adjoining the gate electrode. However, it is not convenient to use nitride overhang structures in some IC processes.
It would be advantageous if an improved silicide process were available to permit the fabrication of shallow junction areas with small leakage currents.
It would be advantageous if a silicidation metal could be formed on selective surfaces to control formation of silicide.
It would be advantageous if the thickness and the thickness tolerances of silicide layers formed on source/drain electrodes could be better controlled to maintain a consistent separation between the silicide and the junction area metallurgical edges.
Accordingly, in a MOS transistor, a method of forming shallow source/drain junctions with low leakage currents has been provided. The method comprises the steps of
a) in a bulk silicon substrate well, forming silicon source/drain regions with an overlying gate electrode. The source/drain regions can be defined using any conventional technique;
b) depositing a layer of metal, having a predetermined metal thickness over the transistor, the metal is typically deposited through a physical vapor deposition (PVD), such as sputtering or evaporation, or even chemical vapor deposition methods (CVD). Possible silicidation metals include Co, Ni, Ti Mo, Ta, W, Cr, Pt, and Pd. When Co and Ni are used, the predetermined thickness of metal is in the range between 50 and 1000 Å,
c) performing a first annealing of the metal deposited in Step b). Co is annealed at a temperature in the range between 300 and 500 degrees C. to partially react the metal with the silicon of the source/drain top surfaces, whereby metal-rich silicide compounds are formed. When Ni is selected, the temperature is in the range between 150 and 400 degrees C. Using either metal, the period of time is in the range between 2 and 20 seconds;
d) removing the metal deposited in Step b) not silicided in Step c), whereby silicide compounds remain on the source/drain top surfaces; and
e) performing a second annealing of the silicide compounds formed in Step c) to complete the reaction of the metal and the silicon, forming a low resistance silicide layer having a silicide layer thickness and silicide layer thickness tolerance overlying the source/drain top surfaces. With Co, the temperature is in the range between 600 and 850 degrees C. and the period of time is in the range between 10 and 60 seconds. With Ni, the temperature is approximately 500 degrees C. and the period of time is in the range between 10 and 30 seconds. The silicide thickness formed is in the range between 100 and 500 Å, and the silicide thickness tolerance is less than 50% of the disilicide thickness. The silicide minimally penetrates into the silicon around the edges of the source/drain top surfaces.
The junction areas can be formed either before, or after silicidation. Either way, the source/drain junction areas have metallurgical edges formed at a junction depth of between 300 and 2000 Å from the source/drain top surfaces.
In some aspects of the invention, a further step follows Step a), and precedes Step b) of:
a
2
) amorphousizing the crystalline structure of the source/drain top surfaces to a depth of 100 to 500 Å, whereby the source/drain top surfaces are prepared for the process of sil
Hsu Sheng Teng
Maa Jer-shen
Peng Chien-Hsiung
Chaudhuri Olik
Kreiger Scott C.
Louie Wai-Sing
Rabdau Matthew D.
Ripma David C.
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